Lesson 1. ROM point: a transistor is a bit

In pictures

After this lesson you will have one point of read-only memory — ROM — and you will see how it stores a bit without power and without latches: a bit is simply whether a transistor is there or not. Along the way we will build the kit's two gates, NOT and AND, — from transistors, like everything in this kit.


1.1. The idea: a bit you cannot erase

In memory made of latches, a bit lives while there is power, and you can overwrite it. In ROM (read-only memory) the contents are set when the chip is made: in the right place a transistor is put in — or it is not. This is how terminal fonts, calculator programs and game programs were stored.

One ROM point is where two wires cross:

  • the row is the select wire: we put 1 on it when we want to read;
  • the column is the bit wire: a resistor always pulls it weakly to 1;
  • the transistor (if it is there) connects the column to ground when the row is selected, and pulls the column down to 0 — it is stronger than the resistor.
bit = 1: a transistorVCCRblrow selected = 1NGND = 0NOTQ = 1column = 0pulled by the transistorbit = 0: emptyVCCRblrow selected = 1no transistorNOTQ = 0column = 1held by the resistor
One point of the ROM. The row drives the gates, the column is the bit, the resistor on top holds it at 1. With a transistor, the selected row pulls the column down to 0 and NOT turns it into 1. Without one, the column stays 1 and the output is 0.

Select a row: where there is a transistor, the column is 0; where there is none, it is 1. The NOT at the output flips this, and we get the familiar rule: transistor present — 1, no transistor — 0.

A resistor is a part with two legs, a "weak wire": a signal passes through it, but gives way to any real output. In the palette it is an empty rectangle, key X.

1.2. Build

A new empty project. All connections are made with labels: the same name means one wire.

Step 0. The NOT and AND gates — the kit's own chips

Place the power right away (Power → label VCC, Ground → label GND) — inside chips, VCC/GND are shared.

Place the parts on an empty area of the canvas, then fold each gate into a chip. Transistor: gate G on the left, the channel is top and bottom (they are equal). pmos conducts when the gate is 0, nmos when it is 1.

NOT (2 transistors):

PartGate (G)Channel connects
Input port—name I0, output → I0
pmosI0VCC ↔ O0
nmosI0O0 ↔ GND
Output port—name O0, input ← O0

Select these 4 parts (and their labels) → Ctrl+G → in the library, double-click the name → NOT.

AND (6 transistors): "NOT-AND" at node n, then a flip into O0.

PartGate (G)Channel connects
Input port—name I0, output → I0
Input port—name I1, output → I1
pmosI0VCC ↔ n
pmosI1VCC ↔ n
nmosI0n ↔ mid
nmosI1mid ↔ GND
pmosnVCC ↔ O0
nmosnO0 ↔ GND
Output port—name O0, input ← O0

If you already have NOT and AND from the "A Watch and a Game from Gates" kit, use them: their legs are A, B, Y, which is the same as I0, I1, O0 in the tables.

Step 1. Power and the row

PartOutput label
Power (VCC)VCC
Ground (GND)GND
Inputs

Step 2. Column a — the point is there

PartGate (G)Legs / channel connect
Resistor—VCC ↔ a
nmossa ↔ GND
PartI0 (input)O0 (output)
NOTaQa
PartInput
LEDQa

Step 3. Column b — no point

PartLegs connect
ResistorVCC ↔ b
PartI0 (input)O0 (output)
NOTbQb
PartInput
LEDQb

1.3. Check

SwitchLamp QaLamp Qb
s = 0offoffrow not selected — both are silent
s = 1onoffselected: transistor present — 1,
no transistor — 0

Experiment: move the transistor from column a to column b (channel b ↔ GND) — with s = 1, Qb lights up and Qa goes out. This is "reprogramming": the contents of a ROM are just where the transistors are placed.

Common mistake. The resistor is placed between the column and NOT, and is not connected to VCC. Then, when the transistor is off, nothing pulls the column — it "floats", and the lamp turns orange instead of going out. One leg of the resistor goes to VCC.


Paste for lesson 1 (Cmd+I)

Into a new empty project: the kit's gates and the ROM point.

chip NOT {  portIn(I0)  portOut(O0)  pmos(I0, VCC, O0)  nmos(I0, O0, GND)} chip AND {  portIn(I0)  portIn(I1)  portOut(O0)  pmos(I0, VCC, n)  pmos(I1, VCC, n)  nmos(I0, n, mid)  nmos(I1, mid, GND)  pmos(n, VCC, O0)  nmos(n, O0, GND)} power(VCC)ground(GND)input(s) resistor(VCC, a)nmos(s, a, GND)NOT(I0=a, O0=Qa)led(Qa) resistor(VCC, b)NOT(I0=b, O0=Qb)led(Qb)

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