Lesson 0. Gates from transistors: for those who start from scratch

In pictures

This lesson is optional. If the gates NOT, NAND, NOR, AND, OR, XOR are already in your library from another kit of the series, go straight to lesson 1. If you want to build everything yourself from transistors, start here: six gates that the whole card is then built from.


0.1. The idea: a transistor is a switch

In the simulator a transistor is a switch with three pins: the gate G controls whether the channel between the top and bottom pins conducts. nmos conducts when G = 1, pmos when G = 0. The pair "P on top to VCC, N below to GND" with a common gate is a NOT: its output is always the opposite of its input. NAND and NOR are built from such pairs, and all the other gates from them.

0.2. Building

A lesson for those who build everything from scratch. If the gates NOT, NAND, NOR, AND, OR, XOR are already in your library (from the "Fractal Machine", "Character Generator", "How a CPU Counts" or "A Watch and a Game from Gates" kits), you can skip this lesson.

A new empty project. First place the power: Power → label VCC, Ground → label GND (they are shared inside chips). Each gate is built on an empty spot of the canvas, then select its parts with their labels → Ctrl+G → double-click the name in the library → the chip name. Transistor: the gate G on the left, the channel is top and bottom (interchangeable); pmos conducts when the gate is 0, nmos when it is 1.

Gates from the "A Watch and a Game from Gates" kit will do too: their pins A, B, Y are the same as I0, I1, O0 in the tables.

Step 1. NOT — flip: 1 → 0, 0 → 1

PartGate (G)Channel connects
Input port—name I0, out → I0
pmosI0VCC ↔ O0
nmosI0O0 ↔ GND
Output port—name O0, in ← O0

Ctrl+G → name NOT.

A common mistake. Swapping N and P: if N is on top (to VCC) and P at the bottom (to GND), the gate does not flip but repeats its input. P always goes on top, N at the bottom. The type changes with Alt + click on the transistor (on a Mac — ⌥ or ⌘ + click); a plain click does not change it.

Step 2. NAND — NOT-AND: 0 only when both inputs are 1

PartGate (G)Channel connects
Input port—name I0, out → I0
Input port—name I1, out → I1
pmosI0VCC ↔ O0
pmosI1VCC ↔ O0
nmosI0O0 ↔ mid
nmosI1mid ↔ GND
Output port—name O0, in ← O0

Ctrl+G → name NAND.

Step 3. NOR — NOT-OR: 1 only when both inputs are 0

PartGate (G)Channel connects
Input port—name I0, out → I0
Input port—name I1, out → I1
pmosI0VCC ↔ mid
pmosI1mid ↔ O0
nmosI0O0 ↔ GND
nmosI1O0 ↔ GND
Output port—name O0, in ← O0

Ctrl+G → name NOR.

Step 4. AND: NAND at node n, then a flip

PartGate (G)Channel connects
Input port—name I0, out → I0
Input port—name I1, out → I1
pmosI0VCC ↔ n
pmosI1VCC ↔ n
nmosI0n ↔ mid
nmosI1mid ↔ GND
pmosnVCC ↔ O0
nmosnO0 ↔ GND
Output port—name O0, in ← O0

Ctrl+G → name AND.

Step 5. OR: NOR at node n, then a flip

PartGate (G)Channel connects
Input port—name I0, out → I0
Input port—name I1, out → I1
pmosI0VCC ↔ mid
pmosI1mid ↔ n
nmosI0n ↔ GND
nmosI1n ↔ GND
pmosnVCC ↔ O0
nmosnO0 ↔ GND
Output port—name O0, in ← O0

Ctrl+G → name OR.

Step 6. XOR — "at least one, but not both"

From ready gates: XOR = AND(OR, NAND).

PartI0I1O0 (output)
Input port——I0
Input port——I1
ORI0I1o
NANDI0I1n
ANDonO0
Output portO0——

Ctrl+G → name XOR.

0.3. Check

Select a chip in the library or on the canvas and press T — the truth table opens. Compare:

ChipO0 at I1 I0 = 00 01 10 11
NOT(one input I0) 1 0
NAND1 1 1 0
NOR1 0 0 0
AND0 0 0 1
OR0 1 1 1
XOR0 1 1 0

Lesson 0 paste (Cmd+I)

The paste contains only chip definitions: the gates appear in the library, the canvas does not change.

# Lesson 0 — gates from transistors: NOT, NAND, NOR, AND, OR, XOR (chip definitions only).chip NOT {  portIn(I0)  portOut(O0)  pmos(I0, VCC, O0)  nmos(I0, O0, GND)} chip NAND {  portIn(I0)  portIn(I1)  portOut(O0)  pmos(I0, VCC, O0)  pmos(I1, VCC, O0)  nmos(I0, O0, mid)  nmos(I1, mid, GND)} chip NOR {  portIn(I0)  portIn(I1)  portOut(O0)  pmos(I0, VCC, mid)  pmos(I1, mid, O0)  nmos(I0, O0, GND)  nmos(I1, O0, GND)} chip AND {  portIn(I0)  portIn(I1)  portOut(O0)  pmos(I0, VCC, n)  pmos(I1, VCC, n)  nmos(I0, n, mid)  nmos(I1, mid, GND)  pmos(n, VCC, O0)  nmos(n, O0, GND)} chip OR {  portIn(I0)  portIn(I1)  portOut(O0)  pmos(I0, VCC, mid)  pmos(I1, mid, n)  nmos(I0, n, GND)  nmos(I1, n, GND)  pmos(n, VCC, O0)  nmos(n, O0, GND)} chip XOR {  portIn(I0)  portIn(I1)  portOut(O0)  OR(I0, I1, o)  NAND(I0, I1, n)  AND(o, n, O0)}

¿No te sale? Algo no funciona →