Lesson 3. The CD4029B counter

After this lesson the library has a real CD4029B counter: it counts up and down, in binary (0–15) and decade (0–9), can be set to any number and reports a carry. Inside is the logic diagram from the TI datasheet, gate for gate.

3.1. Idea: which bit to flip

Not all flip-flops flip on the clock, only those allowed to:

• up: a bit flips if all lower bits are 1 (0111 + 1 = 1000);
• down: a bit flips if all lower bits are 0 (1000 − 1 = 0111);
• in decade mode 9 is followed by 0, not 10 — that is what the signals bout and md are for.

TI draws the logic around the flip-flops on two pages, and the wires that go across are named with letters A–L. We kept these names.

3.2. Idea: controlling the counter

• PE = 1 — load J4 J3 J2 J1 at once (preset), the clock is blocked;
• CI = 0 — counting allowed, CI = 1 — stopped;
• BD: 1 — binary, 0 — decade; UD: 1 — up, 0 — down;
• CO = 0 — carry: up — at 15 (or 9), down — at 0. CO of one counter → CI of the next — that is how two CD4029 make two digits.

3.3. Idea: the bubbles on the TI drawing

The TI drawing has many gates with bubbles on their inputs. A bubble is a NOT. An "AND" with bubbles on all inputs is a NOR: it gives 1 only when all inputs are 0. So in the table there are NOR, NOR3, NOR4 instead, and where there is a bubble on one input — a separate NOT.

Building with wires — the whole circuit as one drawing, laid out like TI:

3.4. Build

The same project. The library needs the lesson 0 gates and FF4029 (lesson 2).

Step 1. Chip NOR3 — NOR with 3 inputs from 6 transistors

The opposite of NAND3: three pmos in a chain from VCC to the output, three nmos in parallel from the output to GND. The output is 1 only when all inputs are 0.

Ctrl+G → name NOR3. Legs: inputs A, B, C; outputs Y.

Step 2. Chip NOR4 — NOR with 4 inputs from 8 transistors

Like NOR3, one more input.

Ctrl+G → name NOR4. Legs: inputs A, B, C, D; outputs Y.

Step 3. Chip CD4029 — up/down counter, binary/decade

Package pins from the TI datasheet: 1 PE, 2 Q4, 3 J4, 4 J1, 5 CI, 6 Q1, 7 CO, 9 BD, 10 UD, 11 Q2, 12 J2, 13 J3, 14 Q3, 15 CLOCK; 8 — VSS, 16 — VDD. Inside — TI Fig. 9 gate for gate; the names A–L are as at TI. The TI bubbles on inputs are already turned into gates: "AND" with bubbles on all inputs = NOR, NOR3, NOR4; a bubble on one input = a separate NOT. Building with wires — the whole drawing is at the start of the lesson.

Ctrl+G → name CD4029. Legs: inputs PE, J4, J1, CI, BD, UD, J2, J3, CLOCK; outputs Q4, Q1, CO, Q2, Q3.

Step 4. Probe: switches and generator

Clock — 1Hz.

Step 5. Counter

Step 6. Lamps

Place the lamps in the order Q4 Q3 Q2 Q1 — they read as a binary number.

3.5. Check

Lamps Q4 Q3 Q2 Q1 — the number in binary; CO — carry, lit while there is no carry (active 0).

1. Clock — 1Hz. J4 J3 J2 J1 = 0101, PE = 1: the lamps show 0101 (5) at once, the clock does not count.
2. PE = 0, CI = 0, BD = 1, UD = 1: counting up 5, 6 … 15, 0 … At 15 CO goes out.
3. BD = 0 — decade: 0 … 9, 0. CO goes out at 9.
4. UD = 0 — down: 9, 8 … 0, 9. CO goes out at 0.
5. CI = 1 — counting stops, CO is lit.

After the check delete the probe — NOR3, NOR4, CD4029 stay in the library.

Lesson 3 paste (Cmd+I)

You need the lesson 0 gates and FF4029 (lesson 2).

# Lesson 3 — CD4029B: an up/down, binary/decade counter with preset (TI Fig. 9 gate for gate).# Paste: Cmd+I into the same project (lesson 0 gates and FF4029 from lesson 2 needed). chip NOR3 {  portIn(A)  portIn(B)  portIn(C)  portOut(Y)  pmos(A, VCC, p1)  pmos(B, p1, p2)  pmos(C, p2, Y)  nmos(A, Y, GND)  nmos(B, Y, GND)  nmos(C, Y, GND)} chip NOR4 {  portIn(A)  portIn(B)  portIn(C)  portIn(D)  portOut(Y)  pmos(A, VCC, p1)  pmos(B, p1, p2)  pmos(C, p2, p3)  pmos(D, p3, Y)  nmos(A, Y, GND)  nmos(B, Y, GND)  nmos(C, Y, GND)  nmos(D, Y, GND)} chip CD4029 {  portIn(PE)  portIn(J4)  portIn(J1)  portIn(CI)  portIn(BD)  portIn(UD)  portIn(J2)  portIn(J3)  portIn(CLOCK)  portOut(Q4)  portOut(Q1)  portOut(CO)  portOut(Q2)  portOut(Q3)  NOT(BD, nBD)  NOT(nBD, A)  NOT(PE, E)  NOT(CI, nCI)  NOT(UD, nUD)  NOT(nUD, U)  NOT(CLOCK, nCLK)  NAND(E, nCLK, ncl)  NOT(ncl, CL)  NOT(J1, j1)  NOT(J2, j2)  NOT(J3, j3)  NOT(J4, j4)  FF4029(PE=E, J=j1, TE=CI, CL=CL, Q=q1, QN=q1n)  FF4029(PE=E, J=j2, TE=te2, CL=CL, Q=D, QN=J)  FF4029(PE=E, J=j3, TE=G, CL=CL, Q=B, QN=I)  FF4029(PE=E, J=j4, TE=te4, CL=CL, Q=C, QN=q4n)  NAND3(A=nCI, B=nUD, C=q1n, Y=nf)  NOT(nf, F)  NAND3(A=q1, B=nCI, C=U, Y=nl)  NOT(nl, L)  NOR4(A=A, B=B, C=C, D=D, Y=bout)  NOT(bout, nbout)  AND(nbout, F, ta)  NAND(nBD, C, md)  AND(L, md, tb)  NOR(ta, tb, te2)  NOR(bout, D, te_)  AND(F, te_, tg)  AND(D, L, tf)  NOR(tg, tf, G)  # H  NOR(J, I, th)  NOT(md, nmd)  OR(th, nmd, H)  NOR(D, B, tp)  AND(F, tp, tq)  AND(H, L, tr)  NOR(tq, tr, te4)  NOR3(A=B, B=D, C=C, Y=tv)  AND(F, tv, tw)  NOT(A, an)  OR(an, th, tt)  AND(C, tt, tu)  AND(L, tu, tx)  NOR(tw, tx, co0)  NOT(co0, co1)  NOT(co1, CO)  NOT(q1, o1)  NOT(o1, Q1)  NOT(D, o2)  NOT(o2, Q2)  NOT(B, o3)  NOT(o3, Q3)  NOT(C, o4)  NOT(o4, Q4)} power(VCC)ground(GND)input(PE)input(J1)input(J2)input(J3)input(J4)input(CI)input(BD)input(UD)clock(CLOCK)CD4029(PE=PE, J1=J1, J2=J2, J3=J3, J4=J4, CI=CI, BD=BD, UD=UD, CLOCK=CLOCK, Q1=Q1, Q2=Q2, Q3=Q3, Q4=Q4, CO=CO)led(CLOCK)led(Q4)led(Q3)led(Q2)led(Q1)led(CO)