Lesson 1. The ATM processor: the same one as in the card

After this lesson the ATM has a heart — a processor, a ROM with the program and a bus over which the processor reads the devices. We do not build the processor again: we copy it from our card and fold it into the CPU chip. A light runs along the lamps — the same one as in lesson 2 of the card.

1.1. The idea: one processor — different machines

The card processor knows nothing about cards. It can add, compare, jump and read or write cells by address — and that is all. What makes it a card is the program and what is connected to its addresses: the matrix with the key, the IO wire. Put the same processor into an ATM, connect a keypad, a screen and a bank — and it is an ATM. Real machines work this way: the same processor sits in a washing machine, in a keyboard and in an ATM.

The processor is the same. The card program and its matrix make it a card; the ATM program and its devices make it an ATM.

1.2. The idea: device addresses

The processor has an 8-bit address. Cells 0–7 are its RAM (inside CPU). All the ATM devices live at addresses where bit 4 = 1: this way selecting them never touches the RAM. A device is selected only by commands with data — LD, ST, ADD, CMP… A number in the command (LD #26) and a jump address (JMP 26) leave the devices alone.

Address	Read	Write
$00–$07	processor RAM	processor RAM
$10	the bank key, byte by byte (lesson 4)	—
$18, $19	balances of accounts 1 and 2 (les. 4)	balances of accounts 1 and 2
$1A	keypad: pressed + code (lesson 2)	"pressed" — clear
$1B	a random number (lesson 5)	—
$1C	the card answer (lesson 5)	a byte for the card
$1D	the "wait" lamp	SEND, card reset
$1E	—	screen words (lesson 3)
$1F	—	the account for the bank (lesson 4)
$30–$37	—	screen digits (lesson 3)
$3A	key code × 16 (lesson 2)	—

1.3. The idea: the read bus — an OR of all devices

What to read, the processor learns on the legs ext0–ext7. Every device feeds its byte through AND with its own select signal: an unselected one gives zeros. All the bytes meet in OR8 — the output is only the byte of the selected device. Inside CPU this byte goes through OR with the RAM once more: din = ram | ext. While there are no devices yet, ext is clean zeros, and the processor works as in the card.

The read bus. Every device feeds its byte through AND with its own select: unselected ones give zeros, so OR8 passes only the selected one. Inside the processor this byte goes through OR with the RAM once more. (Every line here is eight wires, one per bit.)

1.4. Building

The same project where "The Payment Card" is built: on the canvas are CARD, CARD 2, TERM, the Clock generator, the switches RST and FAC. We build the ATM to the right of them.

Step 1. A copy of the card's core

The ATM's processor is the same as the card's. We take it from the card instead of building it again.

CARD → "Edit" → select all → copy → exit without saving (the card itself does not change) → paste onto a free spot of the canvas, to the right of the card. From here on we work only with the copy.

Step 2. Remove what only the card has

The copy keeps the core: the ALU, register A, the flags, PC, the stack, the command decoder, the RAM. We remove what belongs to the card: the ROM with its program (the ATM will have its own, outside the processor), the personal data (the matrix), the attempt counter TRY, the IO port, the eight port pins and the old read ORs din (we replace them in step 3). The labels next to the deleted parts can stay — they get in nobody's way.

Element	How to find	Action
Memory (RAM)	the card's ROM	delete
NOT	whose output = nir3	delete
NOT	whose output = nir2	delete
AND	whose output = selP	delete
AND3	whose output = selTRY	delete
AND3	whose output = selIO	delete
AND	whose output = pr0	delete
AND	whose output = pr1	delete
AND	whose output = pr2	delete
AND	whose output = pr3	delete
AND	whose output = pr4	delete
AND	whose output = pr5	delete
AND	whose output = pr6	delete
Resistor	between VCC and pb0	delete
Resistor	between VCC and pb1	delete
Resistor	between VCC and pb2	delete
Resistor	between VCC and pb3	delete
Resistor	between VCC and pb4	delete
Resistor	between VCC and pb5	delete
Resistor	between VCC and pb6	delete
Resistor	between VCC and pb7	delete
NOT	whose output = pq0	delete
NOT	whose output = pq1	delete
NOT	whose output = pq2	delete
NOT	whose output = pq3	delete
NOT	whose output = pq4	delete
NOT	whose output = pq5	delete
NOT	whose output = pq6	delete
NOT	whose output = pq7	delete
AND	whose output = t0	delete
AND	whose output = t1	delete
AND	whose output = io0	delete
OR4	whose output = din0	delete
OR3	whose output = din1	delete
OR	whose output = din2	delete
OR	whose output = din3	delete
OR	whose output = din4	delete
OR	whose output = din5	delete
OR	whose output = din6	delete
OR	whose output = din7	delete
AND	whose output = wOUT	delete
RBIT	whose output = pull	delete
nmos	gate pull, drain IO	delete
NOT	whose output = nFAC	delete
AND	whose output = wTRY	delete
RBIT	whose output = try0	delete
RBIT	whose output = try1	delete
nmos	gate pr0, drain pb0	delete
nmos	gate pr1, drain pb1	delete
nmos	gate pr1, drain pb4	delete
nmos	gate pr2, drain pb2	delete
nmos	gate pr2, drain pb4	delete
nmos	gate pr2, drain pb5	delete
nmos	gate pr3, drain pb1	delete
nmos	gate pr3, drain pb3	delete
nmos	gate pr3, drain pb4	delete
nmos	gate pr4, drain pb0	delete
nmos	gate pr4, drain pb1	delete
nmos	gate pr4, drain pb6	delete
nmos	gate pr4, drain pb7	delete
nmos	gate pr5, drain pb0	delete
nmos	gate pr5, drain pb1	delete
nmos	gate pr5, drain pb2	delete
nmos	gate pr5, drain pb4	delete
nmos	gate pr6, drain pb1	delete
nmos	gate pr6, drain pb2	delete
nmos	gate pr6, drain pb3	delete
nmos	gate pr6, drain pb7	delete
nmos	gate pr3, drain pb6	delete
Input port	name C1	delete
Input port	name C2	delete
Input port	name C3	delete
Input port	name C4	delete
Output port	name C7	delete
Output port	name C8	delete
Input port	name C5	delete
Input port	name C6	delete

Step 3. Reading: RAM or outside

The processor reads either its own RAM (addresses 0–7) or whatever comes from outside on ext0–ext7 — from the ATM's devices. Paste 01-cpu-a.netlist.txt (Cmd+I) — these 8 ORs and the ports of step 4; place them next to the copy.

Part	Pin	Label
OR	I0 I1 O0	ram0 ext0 din0
OR	I0 I1 O0	ram1 ext1 din1
OR	I0 I1 O0	ram2 ext2 din2
OR	I0 I1 O0	ram3 ext3 din3
OR	I0 I1 O0	ram4 ext4 din4
OR	I0 I1 O0	ram5 ext5 din5
OR	I0 I1 O0	ram6 ext6 din6
OR	I0 I1 O0	ram7 ext7 din7

Step 4. The processor's pins — ports

Port name = label. Inputs: clock, reset, the command word from the ROM (ir0–ir15), reading from outside (ext0–ext7). Outputs: the command address for the ROM (pc0–pc7), register A (acc0–acc7 — it is what gets written to devices), oST — "command ST", a write to a device.

Part	Pin	Label
Input port	name CLK	CLK
Input port	name RST	RST
Input port	name ir0	ir0
Input port	name ir1	ir1
Input port	name ir2	ir2
Input port	name ir3	ir3
Input port	name ir4	ir4
Input port	name ir5	ir5
Input port	name ir6	ir6
Input port	name ir7	ir7
Input port	name ir8	ir8
Input port	name ir9	ir9
Input port	name ir10	ir10
Input port	name ir11	ir11
Input port	name ir12	ir12
Input port	name ir13	ir13
Input port	name ir14	ir14
Input port	name ir15	ir15
Input port	name ext0	ext0
Input port	name ext1	ext1
Input port	name ext2	ext2
Input port	name ext3	ext3
Input port	name ext4	ext4
Input port	name ext5	ext5
Input port	name ext6	ext6
Input port	name ext7	ext7
Output port	name pc0	pc0
Output port	name pc1	pc1
Output port	name pc2	pc2
Output port	name pc3	pc3
Output port	name pc4	pc4
Output port	name pc5	pc5
Output port	name pc6	pc6
Output port	name pc7	pc7
Output port	name acc0	acc0
Output port	name acc1	acc1
Output port	name acc2	acc2
Output port	name acc3	acc3
Output port	name acc4	acc4
Output port	name acc5	acc5
Output port	name acc6	acc6
Output port	name acc7	acc7
Output port	name oST	oST

Step 5. Fold into a chip

Frame-select the copy, the 8 ORs and the ports → Ctrl+G → name CPU. A CPU chip without labels stays on the canvas — delete it: the chip is already in the library, and in step 7 it comes in with labels on all its pins.

Step 6. The ATM's ROM

Memory (RAM) from the palette, ⚙: 256 words, 16b data, 16b addr, CLR off (like the card's ROM in lesson 2). Pins A8–A15, WE, CLK and all D0–D15 go to GND.

Part	Pin	Label
Memory (RAM) ROM	A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15	pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 GND GND GND GND GND GND GND GND ir0 ir1 ir2 ir3 ir4 ir5 ir6 ir7 ir8 ir9 ir10 ir11 ir12 ir13 ir14 ir15

Step 7. The processor, device addresses, the read bus

Paste 01-cpu-b.netlist.txt (Cmd+I). The ATM's devices live at addresses with bit 4 = 1 (past the processor's RAM): the decoder lights the select wire sel…, and ST to the selected device lights the write wire st…. Everything the processor reads from outside meets through ORs in ext0–ext7 — each through an AND with its own select. The devices themselves are not there yet: their labels (key, bal, rn, kq…) are empty for now, but an AND with an unselected device gives a clean 0. A device is selected only by commands with data — not by a "number" (LD #16) and not by a jump.

Part	Pin	Label
CPU	CLK RST ir0 ir1 ir2 ir3 ir4 ir5 ir6 ir7 ir8 ir9 ir10 ir11 ir12 ir13 ir14 ir15 ext0 ext1 ext2 ext3 ext4 ext5 ext6 ext7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 acc0 acc1 acc2 acc3 acc4 acc5 acc6 acc7 oST	CLK RST ir0 ir1 ir2 ir3 ir4 ir5 ir6 ir7 ir8 ir9 ir10 ir11 ir12 ir13 ir14 ir15 ext0 ext1 ext2 ext3 ext4 ext5 ext6 ext7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 acc0 acc1 acc2 acc3 acc4 acc5 acc6 acc7 oST
NOT	I0 O0	RST nR
OR3	A B C Y	ir12 ir13 ir14 op9
AND	I0 I1 O0	ir15 op9 isJ
NOR	I0 I1 O0	isJ ir11 nJI
AND	I0 I1 O0	ir4 nJI dev
NOT	I0 O0	ir5 nir5
NOT	I0 O0	ir3 nir3
AND	I0 I1 O0	dev nir5 s1x
AND	I0 I1 O0	dev ir5 s3x
AND	I0 I1 O0	s1x nir3 s10
AND	I0 I1 O0	s1x ir3 s18
AND	I0 I1 O0	s3x nir3 s30
AND	I0 I1 O0	s3x ir3 s38
DEC8	I0 I1 I2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7	ir0 ir1 ir2 a0 a1 a2 a3 a4 a5 a6 a7
AND	I0 I1 O0	s10 a0 selKEYB
AND	I0 I1 O0	s18 a0 selBAL1
AND	I0 I1 O0	s18 a1 selBAL2
AND	I0 I1 O0	s18 a2 selKEY
AND	I0 I1 O0	s18 a3 selRND
AND	I0 I1 O0	s18 a4 selTD
AND	I0 I1 O0	s18 a5 selTC
AND	I0 I1 O0	s18 a6 selWRD
AND	I0 I1 O0	s18 a7 selACCT
AND	I0 I1 O0	s30 a0 selD0
AND	I0 I1 O0	s30 a1 selD1
AND	I0 I1 O0	s30 a2 selD2
AND	I0 I1 O0	s30 a3 selD3
AND	I0 I1 O0	s30 a4 selD4
AND	I0 I1 O0	s30 a5 selD5
AND	I0 I1 O0	s30 a6 selD6
AND	I0 I1 O0	s30 a7 selD7
AND	I0 I1 O0	s38 a2 selKEYH
AND	I0 I1 O0	oST selBAL1 stBAL1
AND	I0 I1 O0	oST selBAL2 stBAL2
AND	I0 I1 O0	oST selKEY stKEY
AND	I0 I1 O0	oST selTD stTD
AND	I0 I1 O0	oST selTC stTC
AND	I0 I1 O0	oST selWRD stWRD
AND	I0 I1 O0	oST selACCT stACCT
AND	I0 I1 O0	oST selD0 stD0
AND	I0 I1 O0	oST selD1 stD1
AND	I0 I1 O0	oST selD2 stD2
AND	I0 I1 O0	oST selD3 stD3
AND	I0 I1 O0	oST selD4 stD4
AND	I0 I1 O0	oST selD5 stD5
AND	I0 I1 O0	oST selD6 stD6
AND	I0 I1 O0	oST selD7 stD7
AND	I0 I1 O0	kq0 selKEYB eq0
AND	I0 I1 O0	bal1_0 selBAL1 eb1_0
AND	I0 I1 O0	bal2_0 selBAL2 eb2_0
AND	I0 I1 O0	key0 selKEY ek0
AND	I0 I1 O0	rn0 selRND er0
AND	I0 I1 O0	sr0 selTD es0
AND	I0 I1 O0	lamp selTC elp
OR8	A B C D E F G H Y	eq0 eb1_0 eb2_0 ek0 er0 es0 elp GND ext0
AND	I0 I1 O0	kq1 selKEYB eq1
AND	I0 I1 O0	bal1_1 selBAL1 eb1_1
AND	I0 I1 O0	bal2_1 selBAL2 eb2_1
AND	I0 I1 O0	key1 selKEY ek1
AND	I0 I1 O0	rn1 selRND er1
AND	I0 I1 O0	sr1 selTD es1
OR8	A B C D E F G H Y	eq1 eb1_1 eb2_1 ek1 er1 es1 GND GND ext1
AND	I0 I1 O0	kq2 selKEYB eq2
AND	I0 I1 O0	bal1_2 selBAL1 eb1_2
AND	I0 I1 O0	bal2_2 selBAL2 eb2_2
AND	I0 I1 O0	key2 selKEY ek2
AND	I0 I1 O0	rn2 selRND er2
AND	I0 I1 O0	sr2 selTD es2
OR8	A B C D E F G H Y	eq2 eb1_2 eb2_2 ek2 er2 es2 GND GND ext2
AND	I0 I1 O0	kq3 selKEYB eq3
AND	I0 I1 O0	bal1_3 selBAL1 eb1_3
AND	I0 I1 O0	bal2_3 selBAL2 eb2_3
AND	I0 I1 O0	key3 selKEY ek3
AND	I0 I1 O0	rn3 selRND er3
AND	I0 I1 O0	sr3 selTD es3
OR8	A B C D E F G H Y	eq3 eb1_3 eb2_3 ek3 er3 es3 GND GND ext3
AND	I0 I1 O0	kq4 selKEYB eq4
AND	I0 I1 O0	bal1_4 selBAL1 eb1_4
AND	I0 I1 O0	bal2_4 selBAL2 eb2_4
AND	I0 I1 O0	key0 selKEYH ek4
AND	I0 I1 O0	rn4 selRND er4
AND	I0 I1 O0	sr4 selTD es4
OR8	A B C D E F G H Y	eq4 eb1_4 eb2_4 ek4 er4 es4 GND GND ext4
AND	I0 I1 O0	kq5 selKEYB eq5
AND	I0 I1 O0	bal1_5 selBAL1 eb1_5
AND	I0 I1 O0	bal2_5 selBAL2 eb2_5
AND	I0 I1 O0	key1 selKEYH ek5
AND	I0 I1 O0	rn5 selRND er5
AND	I0 I1 O0	sr5 selTD es5
OR8	A B C D E F G H Y	eq5 eb1_5 eb2_5 ek5 er5 es5 GND GND ext5
AND	I0 I1 O0	kq6 selKEYB eq6
AND	I0 I1 O0	bal1_6 selBAL1 eb1_6
AND	I0 I1 O0	bal2_6 selBAL2 eb2_6
AND	I0 I1 O0	key2 selKEYH ek6
AND	I0 I1 O0	rn6 selRND er6
AND	I0 I1 O0	sr6 selTD es6
OR8	A B C D E F G H Y	eq6 eb1_6 eb2_6 ek6 er6 es6 GND GND ext6
AND	I0 I1 O0	kq7 selKEYB eq7
AND	I0 I1 O0	bal1_7 selBAL1 eb1_7
AND	I0 I1 O0	bal2_7 selBAL2 eb2_7
AND	I0 I1 O0	key3 selKEYH ek7
AND	I0 I1 O0	down selKEY edn
AND	I0 I1 O0	rn7 selRND er7
AND	I0 I1 O0	sr7 selTD es7
OR8	A B C D E F G H Y	eq7 eb1_7 eb2_7 ek7 edn er7 es7 GND ext7
LED	in	acc7
LED	in	acc6
LED	in	acc5
LED	in	acc4
LED	in	acc3
LED	in	acc2
LED	in	acc1
LED	in	acc0
Display	⚙	width 8, DEC, bus pc

Step 8. The program in the ROM

⚙ on ROM → ⬆ → 02-lights.rom.json (the lights from lesson 2 of the card). Clock — click the body until 2Hz.

1.5. Check

Reset: turn RST on for one or two clocks (display PC = 0) and off. The generator steps by itself.

The display is the command number (PC, the address in the ROM), the eight lamps are register A: the light runs along the lamps, and the display shows which command is running now. The program 02-lights:

Clock	Display PC	Command	A	Lamps acc7…acc0	What you see
1	0	LD #1	1	○○○○○○○●
2	1	LD #2	2	○○○○○○●○
3	2	LD #4	4	○○○○○●○○
4	3	LD #8	8	○○○○●○○○
5	4	LD #16	16	○○○●○○○○
6	5	LD #32	32	○○●○○○○○
7	6	LD #64	64	○●○○○○○○
8	7	LD #128	128	●○○○○○○○	the light reached the edge
9	8	CALL 17	128	●○○○○○○○	the display jumps to 17
10	17	LD #255	255	●●●●●●●●	flash
11	18	LD #0	0	○○○○○○○○
12	19	RET	0	○○○○○○○○	the display returns to 9
13	9	LD #64	64	○●○○○○○○	the light runs right

Then ⚙ on ROM → ⬆ → 03-shift.rom.json, turn RST on and off: the light runs left through the RAM — one lamp per 3 clocks (ST 0, ADD 0, JNC), after 128 it goes dark for 3 clocks and starts over.

Everything is the same as in lessons 2 and 3 of the card: the processor moved from the card into the ATM whole.
03-shift adds A to a RAM cell: if the light stands still or all are lit — in step 3 the OR inputs are mixed up (ram and ext → din), or one of the read-bus OR8s has an empty pin (it must be GND).
The labels of future devices (key0, bal1_0, rn0, kq0…) are not connected to anything yet — that is how it should be: their sources appear in lessons 2–5. And ext0–ext7 are already clean 0s.

CPU is in the library, the board is not folded — the keyboard, screen, bank and card port will be added to it later.

Paste for lesson 1 (`Cmd+I`)

Paste A — next to the copy of the card core (steps 3 and 4), then select everything and Ctrl+G → CPU.

# Lesson 1, paste A — next to the copy of the card core: 8 read ORs and 43 ports; then select all and Ctrl+G -> CPU.OR(ram0, ext0, din0)OR(ram1, ext1, din1)OR(ram2, ext2, din2)OR(ram3, ext3, din3)OR(ram4, ext4, din4)OR(ram5, ext5, din5)OR(ram6, ext6, din6)OR(ram7, ext7, din7) portIn{name=CLK}(CLK)portIn{name=RST}(RST)portIn{name=ir0}(ir0)portIn{name=ir1}(ir1)portIn{name=ir2}(ir2)portIn{name=ir3}(ir3)portIn{name=ir4}(ir4)portIn{name=ir5}(ir5)portIn{name=ir6}(ir6)portIn{name=ir7}(ir7)portIn{name=ir8}(ir8)portIn{name=ir9}(ir9)portIn{name=ir10}(ir10)portIn{name=ir11}(ir11)portIn{name=ir12}(ir12)portIn{name=ir13}(ir13)portIn{name=ir14}(ir14)portIn{name=ir15}(ir15)portIn{name=ext0}(ext0)portIn{name=ext1}(ext1)portIn{name=ext2}(ext2)portIn{name=ext3}(ext3)portIn{name=ext4}(ext4)portIn{name=ext5}(ext5)portIn{name=ext6}(ext6)portIn{name=ext7}(ext7)portOut{name=pc0}(pc0)portOut{name=pc1}(pc1)portOut{name=pc2}(pc2)portOut{name=pc3}(pc3)portOut{name=pc4}(pc4)portOut{name=pc5}(pc5)portOut{name=pc6}(pc6)portOut{name=pc7}(pc7)portOut{name=acc0}(acc0)portOut{name=acc1}(acc1)portOut{name=acc2}(acc2)portOut{name=acc3}(acc3)portOut{name=acc4}(acc4)portOut{name=acc5}(acc5)portOut{name=acc6}(acc6)portOut{name=acc7}(acc7)portOut{name=oST}(oST)

Paste B — onto the canvas, to the right of the cards: the processor with labels, device addresses, the read bus, lamps and the display.

# Lesson 1, paste B — onto the canvas: CPU with labels, device addresses, the read bus, lamps A, display PC. The ROM is placed by hand (step 6).CPU(CLK=CLK, RST=RST, ir0=ir0, ir1=ir1, ir2=ir2, ir3=ir3, ir4=ir4, ir5=ir5, ir6=ir6, ir7=ir7, ir8=ir8, ir9=ir9, ir10=ir10, ir11=ir11, ir12=ir12, ir13=ir13, ir14=ir14, ir15=ir15, ext0=ext0, ext1=ext1, ext2=ext2, ext3=ext3, ext4=ext4, ext5=ext5, ext6=ext6, ext7=ext7, pc0=pc0, pc1=pc1, pc2=pc2, pc3=pc3, pc4=pc4, pc5=pc5, pc6=pc6, pc7=pc7, acc0=acc0, acc1=acc1, acc2=acc2, acc3=acc3, acc4=acc4, acc5=acc5, acc6=acc6, acc7=acc7, oST=oST)NOT(RST, nR) OR3(A=ir12, B=ir13, C=ir14, Y=op9)AND(ir15, op9, isJ)NOR(isJ, ir11, nJI)AND(ir4, nJI, dev)NOT(ir5, nir5)NOT(ir3, nir3)AND(dev, nir5, s1x)AND(dev, ir5, s3x)AND(s1x, nir3, s10)AND(s1x, ir3, s18)AND(s3x, nir3, s30)AND(s3x, ir3, s38)DEC8(I0=ir0, I1=ir1, I2=ir2, Y0=a0, Y1=a1, Y2=a2, Y3=a3, Y4=a4, Y5=a5, Y6=a6, Y7=a7)AND(s10, a0, selKEYB)AND(s18, a0, selBAL1)AND(s18, a1, selBAL2)AND(s18, a2, selKEY)AND(s18, a3, selRND)AND(s18, a4, selTD)AND(s18, a5, selTC)AND(s18, a6, selWRD)AND(s18, a7, selACCT)AND(s30, a0, selD0)AND(s30, a1, selD1)AND(s30, a2, selD2)AND(s30, a3, selD3)AND(s30, a4, selD4)AND(s30, a5, selD5)AND(s30, a6, selD6)AND(s30, a7, selD7)AND(s38, a2, selKEYH)AND(oST, selBAL1, stBAL1)AND(oST, selBAL2, stBAL2)AND(oST, selKEY, stKEY)AND(oST, selTD, stTD)AND(oST, selTC, stTC)AND(oST, selWRD, stWRD)AND(oST, selACCT, stACCT)AND(oST, selD0, stD0)AND(oST, selD1, stD1)AND(oST, selD2, stD2)AND(oST, selD3, stD3)AND(oST, selD4, stD4)AND(oST, selD5, stD5)AND(oST, selD6, stD6)AND(oST, selD7, stD7) AND(kq0, selKEYB, eq0)AND(bal1_0, selBAL1, eb1_0)AND(bal2_0, selBAL2, eb2_0)AND(key0, selKEY, ek0)AND(rn0, selRND, er0)AND(sr0, selTD, es0)AND(lamp, selTC, elp)OR8(A=eq0, B=eb1_0, C=eb2_0, D=ek0, E=er0, F=es0, G=elp, H=GND, Y=ext0)AND(kq1, selKEYB, eq1)AND(bal1_1, selBAL1, eb1_1)AND(bal2_1, selBAL2, eb2_1)AND(key1, selKEY, ek1)AND(rn1, selRND, er1)AND(sr1, selTD, es1)OR8(A=eq1, B=eb1_1, C=eb2_1, D=ek1, E=er1, F=es1, G=GND, H=GND, Y=ext1)AND(kq2, selKEYB, eq2)AND(bal1_2, selBAL1, eb1_2)AND(bal2_2, selBAL2, eb2_2)AND(key2, selKEY, ek2)AND(rn2, selRND, er2)AND(sr2, selTD, es2)OR8(A=eq2, B=eb1_2, C=eb2_2, D=ek2, E=er2, F=es2, G=GND, H=GND, Y=ext2)AND(kq3, selKEYB, eq3)AND(bal1_3, selBAL1, eb1_3)AND(bal2_3, selBAL2, eb2_3)AND(key3, selKEY, ek3)AND(rn3, selRND, er3)AND(sr3, selTD, es3)OR8(A=eq3, B=eb1_3, C=eb2_3, D=ek3, E=er3, F=es3, G=GND, H=GND, Y=ext3)AND(kq4, selKEYB, eq4)AND(bal1_4, selBAL1, eb1_4)AND(bal2_4, selBAL2, eb2_4)AND(key0, selKEYH, ek4)AND(rn4, selRND, er4)AND(sr4, selTD, es4)OR8(A=eq4, B=eb1_4, C=eb2_4, D=ek4, E=er4, F=es4, G=GND, H=GND, Y=ext4)AND(kq5, selKEYB, eq5)AND(bal1_5, selBAL1, eb1_5)AND(bal2_5, selBAL2, eb2_5)AND(key1, selKEYH, ek5)AND(rn5, selRND, er5)AND(sr5, selTD, es5)OR8(A=eq5, B=eb1_5, C=eb2_5, D=ek5, E=er5, F=es5, G=GND, H=GND, Y=ext5)AND(kq6, selKEYB, eq6)AND(bal1_6, selBAL1, eb1_6)AND(bal2_6, selBAL2, eb2_6)AND(key2, selKEYH, ek6)AND(rn6, selRND, er6)AND(sr6, selTD, es6)OR8(A=eq6, B=eb1_6, C=eb2_6, D=ek6, E=er6, F=es6, G=GND, H=GND, Y=ext6)AND(kq7, selKEYB, eq7)AND(bal1_7, selBAL1, eb1_7)AND(bal2_7, selBAL2, eb2_7)AND(key3, selKEYH, ek7)AND(down, selKEY, edn)AND(rn7, selRND, er7)AND(sr7, selTD, es7)OR8(A=eq7, B=eb1_7, C=eb2_7, D=ek7, E=edn, F=er7, G=es7, H=GND, Y=ext7) led(acc7)led(acc6)led(acc5)led(acc4)led(acc3)led(acc2)led(acc1)led(acc0)display{bits=8, base="DEC", busSource="pc"}()

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