Lesson 1. Gates and the half adder: 1 + 1 = 10
In picturesAfter this lesson two lamps will show the sum of two bits: 1 + 1 lights up as 10 — "two" in binary. Along the way we build all the gates of the kit from transistors: NOT, NAND, NOR, AND, OR and XOR. The rest of the kit is built only from them.
1.1. The idea: adding one digit
A binary digit has only two values, so adding one digit is just four cases:
| A | B | carry C | sum S |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 0 |
Look at the columns one at a time:
S = A ⊕ B— lit when exactly one input is lit. That is "exclusive OR",XOR;C = A · B— lit when both are lit. That isAND.
A unit made of XOR and AND is called a half adder (HA). "Half" because it adds two bits but cannot take a carry from the neighbouring digit. The full adder in lesson 2 does that.
The kit's XOR is made of ready gates: "at least one" (OR) and at the same time "not both" (NAND) — XOR = AND(OR, NAND).
1.2. Building
A new empty project. First place the power: Power → label VCC, Ground → label GND (they are shared inside chips). Each gate is built on an empty spot of the canvas, then select its parts with their labels → Ctrl+G → double-click the name in the library → the chip name. Transistor: the gate G on the left, the channel is top and bottom (interchangeable); pmos conducts when the gate is 0, nmos when it is 1.
If you already have NOT and AND from the "Character Generator" kit — use them, they are the same. Gates from the "A Watch and a Game from Gates" kit will do too: their pins A, B, Y are the same as I0, I1, O0 in the tables.
Step 1. NOT — flip: 1 → 0, 0 → 1
| Part | Gate (G) | Channel connects |
|---|---|---|
| Input port | — | name I0, out → I0 |
| pmos | I0 | VCC ↔ O0 |
| nmos | I0 | O0 ↔ GND |
| Output port | — | name O0, in ← O0 |
Ctrl+G → name NOT.
A common mistake. Swapping N and P: if N is on top (to VCC) and P at the bottom (to GND), the gate does not flip but repeats its input. P always goes on top, N at the bottom. The type changes with Alt + click on the transistor (on a Mac — ⌥ or ⌘ + click); a plain click does not change it.
Step 2. NAND — NOT-AND: 0 only when both inputs are 1
| Part | Gate (G) | Channel connects |
|---|---|---|
| Input port | — | name I0, out → I0 |
| Input port | — | name I1, out → I1 |
| pmos | I0 | VCC ↔ O0 |
| pmos | I1 | VCC ↔ O0 |
| nmos | I0 | O0 ↔ mid |
| nmos | I1 | mid ↔ GND |
| Output port | — | name O0, in ← O0 |
Ctrl+G → name NAND.
Step 3. NOR — NOT-OR: 1 only when both inputs are 0
| Part | Gate (G) | Channel connects |
|---|---|---|
| Input port | — | name I0, out → I0 |
| Input port | — | name I1, out → I1 |
| pmos | I0 | VCC ↔ mid |
| pmos | I1 | mid ↔ O0 |
| nmos | I0 | O0 ↔ GND |
| nmos | I1 | O0 ↔ GND |
| Output port | — | name O0, in ← O0 |
Ctrl+G → name NOR.
Step 4. AND: NAND at node n, then a flip
| Part | Gate (G) | Channel connects |
|---|---|---|
| Input port | — | name I0, out → I0 |
| Input port | — | name I1, out → I1 |
| pmos | I0 | VCC ↔ n |
| pmos | I1 | VCC ↔ n |
| nmos | I0 | n ↔ mid |
| nmos | I1 | mid ↔ GND |
| pmos | n | VCC ↔ O0 |
| nmos | n | O0 ↔ GND |
| Output port | — | name O0, in ← O0 |
Ctrl+G → name AND.
Step 5. OR: NOR at node n, then a flip
| Part | Gate (G) | Channel connects |
|---|---|---|
| Input port | — | name I0, out → I0 |
| Input port | — | name I1, out → I1 |
| pmos | I0 | VCC ↔ mid |
| pmos | I1 | mid ↔ n |
| nmos | I0 | n ↔ GND |
| nmos | I1 | n ↔ GND |
| pmos | n | VCC ↔ O0 |
| nmos | n | O0 ↔ GND |
| Output port | — | name O0, in ← O0 |
Ctrl+G → name OR.
Step 6. XOR — "at least one, but not both"
From ready gates: XOR = AND(OR, NAND).
| Part | I0 | I1 | O0 (output) |
|---|---|---|---|
| Input port | — | — | I0 |
| Input port | — | — | I1 |
| OR | I0 | I1 | o |
| NAND | I0 | I1 | n |
| AND | o | n | O0 |
| Output port | O0 | — | — |
Ctrl+G → name XOR.
Step 7. HA — the half adder
The sum of one digit S = A ⊕ B and the carry C = A · B.
| Part | I0 | I1 | O0 (output) |
|---|---|---|---|
| Input port | — | — | A |
| Input port | — | — | B |
| XOR | A | B | S |
| AND | A | B | C |
| Output port | S | — | — |
| Output port | C | — | — |
Ctrl+G → name HA. Chip pins: inputs A, B, outputs S, C.
Step 8. Canvas: switches, half adder, lamps
| Part | Pin | Label |
|---|---|---|
| Input | out | A |
| Input | out | B |
| HA | A B S C | A B S C |
| LED | in | S |
| LED | in | C |
Put the lamps side by side: C on the left, S on the right — that way they read as a binary number.
1.3. Check
| A | B | Lamps C S | Meaning |
|---|---|---|---|
| 0 | 0 | · · | 0 + 0 = 0 |
| 0 | 1 | · ● | 0 + 1 = 1 |
| 1 | 0 | · ● | 1 + 0 = 1 |
| 1 | 1 | ● · | 1 + 1 = 10 (two) |
If S is lit at 1 + 1, check XOR: its NAND must give 0 when both inputs are 1.
Lesson 1 paste (Cmd+I)
A new empty project. The paste places all the gates, the half adder and the lesson setup.
# Lesson 1 — the kit gates from transistors and the half adder HA.chip NOT { portIn(I0) portOut(O0) pmos(I0, VCC, O0) nmos(I0, O0, GND)} chip NAND { portIn(I0) portIn(I1) portOut(O0) pmos(I0, VCC, O0) pmos(I1, VCC, O0) nmos(I0, O0, mid) nmos(I1, mid, GND)} chip NOR { portIn(I0) portIn(I1) portOut(O0) pmos(I0, VCC, mid) pmos(I1, mid, O0) nmos(I0, O0, GND) nmos(I1, O0, GND)} chip AND { portIn(I0) portIn(I1) portOut(O0) pmos(I0, VCC, n) pmos(I1, VCC, n) nmos(I0, n, mid) nmos(I1, mid, GND) pmos(n, VCC, O0) nmos(n, O0, GND)} chip OR { portIn(I0) portIn(I1) portOut(O0) pmos(I0, VCC, mid) pmos(I1, mid, n) nmos(I0, n, GND) nmos(I1, n, GND) pmos(n, VCC, O0) nmos(n, O0, GND)} chip XOR { portIn(I0) portIn(I1) portOut(O0) OR(I0, I1, o) NAND(I0, I1, n) AND(o, n, O0)} chip HA { portIn(A) portIn(B) portOut(S) portOut(C) XOR(A, B, S) AND(A, B, C)} power(VCC)ground(GND)input(A)input(B)HA(A, B, S, C)led(S)led(C)¿No te sale? Algo no funciona →