Kits
›
Transistor Memory
RU
EN
ES
Contents
Before you start
A bit of history: how computers remembered
Lesson 1. Cell and row: a 4-bit word
1.1. The idea: memory is a lot of latches
1.2. The cell: a latch and a "tap"
1.3. The row: 4 cells with shared wires
1.4. Building
1.5. Check
Lesson 1 paste (Cmd+I)
Lesson 2. 16×4 memory: sixteen rows and picking one
2.1. The idea: pick one row out of sixteen
2.2. Why reading uses gates and not a shared wire
2.3. Building
2.4. Check
Lesson 2 paste (Cmd+I)
Lesson 3. 256×4 memory: the same circuit one level up
3.1. The idea: the address splits in half
3.2. The cost
3.3. Building
3.4. Check
Lesson 3 paste (Cmd+I)
Lesson 4. Your own memory in the processor — and the first error
4.1. What is in the machine now and how our memory differs
4.2. Memory at power-on — "whatever"
4.3. Building
4.4. Running it — and the error
4.5. Looking for the cause with the oscilloscope
Lesson 4 paste (Cmd+I)
Lesson 5. Two-phase clock: the write never meets a new address
5.1. The idea: put "new address" and "write" into different slices
5.2. Why it doesn't break now
5.3. Building
5.4. Check
Lesson 5 paste (Cmd+I)
Summary
All the parts
Instructions in pictures
Lesson 3 in pictures
← Back to the lesson: Lesson 3. 256×4 memory: the same circuit one level up
3
256×4 memory
the same circuit one level up: 16 blocks
kh
GW-03
8b
10
mA
4b
9
mD
4b
3
mQ
IN
13×
OUT
4×
DEC16
1×
AND
80×
RAM16x4
16×
2
OR4
20×
0
12×
Q
Q
1×
4b
0
A
3×
∞
Ctrl
+
G
RAM256x4
© 2026 Daniil Khanin · khanin.info · GW-03
23
CANVAS
1
Delete
0
mA0
0
mA1
0
mA2
0
mA3
0
mD0
0
mD1
0
mD2
0
mD3
WE
WE
mWE
RAM16x4
A0
mA0
A1
mA1
A2
mA2
A3
mA3
D0
mD0
D1
mD1
D2
mD2
D3
mD3
WE
mWE
Q0
mQ0
Q1
mQ1
Q2
mQ2
Q3
mQ3
4b
0
mA
4b
0
mD
4b
0
mQ
© 2026 Daniil Khanin · khanin.info · GW-03
24
RAM256x4
2
IN
13×
OUT
4×
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
WE
Q0
Q1
Q2
Q3
3
DEC16
1×
20×
DEC16
I0
A4
I1
A5
I2
A6
I3
A7
Y0
b0
Y1
b1
Y2
b2
Y3
b3
Y4
b4
Y5
b5
Y6
b6
Y7
b7
Y8
b8
Y9
b9
Y10
b10
Y11
b11
Y12
b12
Y13
b13
Y14
b14
Y15
b15
4
AND
3×
9×
AND
A
b0
B
WE
Y
w0
AND
A
b1
B
WE
Y
w1
AND
A
b2
B
WE
Y
w2
© 2026 Daniil Khanin · khanin.info · GW-03
25
RAM256x4 …
5
AND
3×
9×
AND
A
b3
B
WE
Y
w3
AND
A
b4
B
WE
Y
w4
AND
A
b5
B
WE
Y
w5
6
AND
3×
9×
AND
A
b6
B
WE
Y
w6
AND
A
b7
B
WE
Y
w7
AND
A
b8
B
WE
Y
w8
7
AND
3×
9×
AND
A
b9
B
WE
Y
w9
AND
A
b10
B
WE
Y
w10
AND
A
b11
B
WE
Y
w11
© 2026 Daniil Khanin · khanin.info · GW-03
26
RAM256x4 …
8
AND
3×
9×
AND
A
b12
B
WE
Y
w12
AND
A
b13
B
WE
Y
w13
AND
A
b14
B
WE
Y
w14
9
AND
1×
3×
AND
A
b15
B
WE
Y
w15
10
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w0
Q0
m0_0
Q1
m0_1
Q2
m0_2
Q3
m0_3
© 2026 Daniil Khanin · khanin.info · GW-03
27
RAM256x4 …
11
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w1
Q0
m1_0
Q1
m1_1
Q2
m1_2
Q3
m1_3
12
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w2
Q0
m2_0
Q1
m2_1
Q2
m2_2
Q3
m2_3
13
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w3
Q0
m3_0
Q1
m3_1
Q2
m3_2
Q3
m3_3
© 2026 Daniil Khanin · khanin.info · GW-03
28
RAM256x4 …
14
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w4
Q0
m4_0
Q1
m4_1
Q2
m4_2
Q3
m4_3
15
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w5
Q0
m5_0
Q1
m5_1
Q2
m5_2
Q3
m5_3
16
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w6
Q0
m6_0
Q1
m6_1
Q2
m6_2
Q3
m6_3
© 2026 Daniil Khanin · khanin.info · GW-03
29
RAM256x4 …
17
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w7
Q0
m7_0
Q1
m7_1
Q2
m7_2
Q3
m7_3
18
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w8
Q0
m8_0
Q1
m8_1
Q2
m8_2
Q3
m8_3
19
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w9
Q0
m9_0
Q1
m9_1
Q2
m9_2
Q3
m9_3
© 2026 Daniil Khanin · khanin.info · GW-03
30
RAM256x4 …
20
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w10
Q0
m10_0
Q1
m10_1
Q2
m10_2
Q3
m10_3
21
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w11
Q0
m11_0
Q1
m11_1
Q2
m11_2
Q3
m11_3
22
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w12
Q0
m12_0
Q1
m12_1
Q2
m12_2
Q3
m12_3
© 2026 Daniil Khanin · khanin.info · GW-03
31
RAM256x4 …
23
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w13
Q0
m13_0
Q1
m13_1
Q2
m13_2
Q3
m13_3
24
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w14
Q0
m14_0
Q1
m14_1
Q2
m14_2
Q3
m14_3
25
RAM16x4
1×
2
13×
RAM16x4
A0
A0
A1
A1
A2
A2
A3
A3
D0
D0
D1
D1
D2
D2
D3
D3
WE
w15
Q0
m15_0
Q1
m15_1
Q2
m15_2
Q3
m15_3
26
AND
3×
9×
AND
A
m0_0
B
b0
Y
c0_0
AND
A
m0_1
B
b0
Y
c0_1
AND
A
m0_2
B
b0
Y
c0_2
© 2026 Daniil Khanin · khanin.info · GW-03
32
RAM256x4 …
27
AND
3×
9×
AND
A
m0_3
B
b0
Y
c0_3
AND
A
m1_0
B
b1
Y
c1_0
AND
A
m1_1
B
b1
Y
c1_1
28
AND
3×
9×
AND
A
m1_2
B
b1
Y
c1_2
AND
A
m1_3
B
b1
Y
c1_3
AND
A
m2_0
B
b2
Y
c2_0
© 2026 Daniil Khanin · khanin.info · GW-03
33
RAM256x4 …
29
AND
3×
9×
AND
A
m2_1
B
b2
Y
c2_1
AND
A
m2_2
B
b2
Y
c2_2
AND
A
m2_3
B
b2
Y
c2_3
30
AND
3×
9×
AND
A
m3_0
B
b3
Y
c3_0
AND
A
m3_1
B
b3
Y
c3_1
AND
A
m3_2
B
b3
Y
c3_2
31
AND
3×
9×
AND
A
m3_3
B
b3
Y
c3_3
AND
A
m4_0
B
b4
Y
c4_0
AND
A
m4_1
B
b4
Y
c4_1
© 2026 Daniil Khanin · khanin.info · GW-03
34
RAM256x4 …
32
AND
3×
9×
AND
A
m4_2
B
b4
Y
c4_2
AND
A
m4_3
B
b4
Y
c4_3
AND
A
m5_0
B
b5
Y
c5_0
33
AND
3×
9×
AND
A
m5_1
B
b5
Y
c5_1
AND
A
m5_2
B
b5
Y
c5_2
AND
A
m5_3
B
b5
Y
c5_3
34
AND
3×
9×
AND
A
m6_0
B
b6
Y
c6_0
AND
A
m6_1
B
b6
Y
c6_1
AND
A
m6_2
B
b6
Y
c6_2
© 2026 Daniil Khanin · khanin.info · GW-03
35
RAM256x4 …
35
AND
3×
9×
AND
A
m6_3
B
b6
Y
c6_3
AND
A
m7_0
B
b7
Y
c7_0
AND
A
m7_1
B
b7
Y
c7_1
36
AND
3×
9×
AND
A
m7_2
B
b7
Y
c7_2
AND
A
m7_3
B
b7
Y
c7_3
AND
A
m8_0
B
b8
Y
c8_0
37
AND
3×
9×
AND
A
m8_1
B
b8
Y
c8_1
AND
A
m8_2
B
b8
Y
c8_2
AND
A
m8_3
B
b8
Y
c8_3
© 2026 Daniil Khanin · khanin.info · GW-03
36
RAM256x4 …
38
AND
3×
9×
AND
A
m9_0
B
b9
Y
c9_0
AND
A
m9_1
B
b9
Y
c9_1
AND
A
m9_2
B
b9
Y
c9_2
39
AND
3×
9×
AND
A
m9_3
B
b9
Y
c9_3
AND
A
m10_0
B
b10
Y
c10_0
AND
A
m10_1
B
b10
Y
c10_1
40
AND
3×
9×
AND
A
m10_2
B
b10
Y
c10_2
AND
A
m10_3
B
b10
Y
c10_3
AND
A
m11_0
B
b11
Y
c11_0
© 2026 Daniil Khanin · khanin.info · GW-03
37
RAM256x4 …
41
AND
3×
9×
AND
A
m11_1
B
b11
Y
c11_1
AND
A
m11_2
B
b11
Y
c11_2
AND
A
m11_3
B
b11
Y
c11_3
42
AND
3×
9×
AND
A
m12_0
B
b12
Y
c12_0
AND
A
m12_1
B
b12
Y
c12_1
AND
A
m12_2
B
b12
Y
c12_2
43
AND
3×
9×
AND
A
m12_3
B
b12
Y
c12_3
AND
A
m13_0
B
b13
Y
c13_0
AND
A
m13_1
B
b13
Y
c13_1
© 2026 Daniil Khanin · khanin.info · GW-03
38
RAM256x4 …
44
AND
3×
9×
AND
A
m13_2
B
b13
Y
c13_2
AND
A
m13_3
B
b13
Y
c13_3
AND
A
m14_0
B
b14
Y
c14_0
45
AND
3×
9×
AND
A
m14_1
B
b14
Y
c14_1
AND
A
m14_2
B
b14
Y
c14_2
AND
A
m14_3
B
b14
Y
c14_3
46
AND
3×
9×
AND
A
m15_0
B
b15
Y
c15_0
AND
A
m15_1
B
b15
Y
c15_1
AND
A
m15_2
B
b15
Y
c15_2
© 2026 Daniil Khanin · khanin.info · GW-03
39
RAM256x4 …
47
AND
1×
3×
AND
A
m15_3
B
b15
Y
c15_3
48
OR4
2×
10×
OR4
A
c0_0
B
c1_0
C
c2_0
D
c3_0
Y
g0_0
OR4
A
c4_0
B
c5_0
C
c6_0
D
c7_0
Y
g1_0
49
OR4
2×
10×
OR4
A
c8_0
B
c9_0
C
c10_0
D
c11_0
Y
g2_0
OR4
A
c12_0
B
c13_0
C
c14_0
D
c15_0
Y
g3_0
© 2026 Daniil Khanin · khanin.info · GW-03
40
RAM256x4 …
50
OR4
2×
10×
OR4
A
g0_0
B
g1_0
C
g2_0
D
g3_0
Y
Q0
OR4
A
c0_1
B
c1_1
C
c2_1
D
c3_1
Y
g0_1
51
OR4
2×
10×
OR4
A
c4_1
B
c5_1
C
c6_1
D
c7_1
Y
g1_1
OR4
A
c8_1
B
c9_1
C
c10_1
D
c11_1
Y
g2_1
© 2026 Daniil Khanin · khanin.info · GW-03
41
RAM256x4 …
52
OR4
2×
10×
OR4
A
c12_1
B
c13_1
C
c14_1
D
c15_1
Y
g3_1
OR4
A
g0_1
B
g1_1
C
g2_1
D
g3_1
Y
Q1
53
OR4
2×
10×
OR4
A
c0_2
B
c1_2
C
c2_2
D
c3_2
Y
g0_2
OR4
A
c4_2
B
c5_2
C
c6_2
D
c7_2
Y
g1_2
54
OR4
2×
10×
OR4
A
c8_2
B
c9_2
C
c10_2
D
c11_2
Y
g2_2
OR4
A
c12_2
B
c13_2
C
c14_2
D
c15_2
Y
g3_2
© 2026 Daniil Khanin · khanin.info · GW-03
42
RAM256x4 …
55
OR4
2×
10×
OR4
A
g0_2
B
g1_2
C
g2_2
D
g3_2
Y
Q2
OR4
A
c0_3
B
c1_3
C
c2_3
D
c3_3
Y
g0_3
56
OR4
2×
10×
OR4
A
c4_3
B
c5_3
C
c6_3
D
c7_3
Y
g1_3
OR4
A
c8_3
B
c9_3
C
c10_3
D
c11_3
Y
g2_3
57
OR4
2×
10×
OR4
A
c12_3
B
c13_3
C
c14_3
D
c15_3
Y
g3_3
OR4
A
g0_3
B
g1_3
C
g2_3
D
g3_3
Y
Q3
© 2026 Daniil Khanin · khanin.info · GW-03
43
RAM256x4 …
CANVAS
58
Ctrl
+
G
Library
…
Chip N
2×
Library
…
RAM256x4
Enter
RAM256x4
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
WE
Q0
Q1
Q2
Q3
59
0
5×
5×
0
mA0
0
mA1
0
mA2
0
mA3
0
mA4
60
0
5×
5×
0
mA5
0
mA6
0
mA7
0
mD0
0
mD1
© 2026 Daniil Khanin · khanin.info · GW-03
44
CANVAS …
61
0
2×
2×
0
mD2
0
mD3
62
Q
Q
1×
1×
WE
WE
mWE
63
RAM256x4
1×
17×
RAM256x4
A0
mA0
A1
mA1
A2
mA2
A3
mA3
A4
mA4
A5
mA5
A6
mA6
A7
mA7
D0
mD0
D1
mD1
D2
mD2
D3
mD3
WE
mWE
Q0
mQ0
Q1
mQ1
Q2
mQ2
Q3
mQ3
© 2026 Daniil Khanin · khanin.info · GW-03
45
CANVAS …
64
4b
0
A
3×
8b
0
mA
4b
0
mD
4b
0
mQ
65
4b
0
mA
⚙
4b
8b
HEX
PIN
mA
mD
mQ
Enter
8b
00
mA
4b
1
mD
WE
WE
4b
1
mQ
8b
10
mA
4b
3
mD
WE
WE
4b
3
mQ
8b
00
mA
4b
9
mD
4b
1
mQ
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Lesson 3. 256×4 memory: the same circuit one level up