Lesson 2. Flip-flops in a package: 74HC74 and a frequency divider

After this lesson the library has the 74HC74 — two D flip-flops in one package, like the real one — and the canvas has a divider: the lamps blink 2, 4, 8 and 16 times slower than the clock, and the display counts from 0 to 15.

2.1. The idea: a flip-flop with set and reset

A D flip-flop stores D at the moment CP changes from 0 to 1 (the edge). The 74HC74 has two more pins that act at once, without an edge:

• SD = 0 — set: Q = 1;
• RD = 0 — reset: Q = 0.

Both act on a zero — in the datasheet their names have a bar. When they are not needed, they are held at 1. If you put 0 on both at once, both outputs become 1 — that is what the datasheet says, and our chip does the same.

2.2. The idea: six NANDs inside

The classic 7474 has six 3-input NAND gates inside: two hold the "next" value, two catch the edge, two are the output itself. We build it exactly like that. And the 3-input NAND itself is six transistors, as in CMOS: three P in parallel and three N in a chain.

2.3. The idea: a divider is a flip-flop that flips

If you feed its own Q̄ to D, the flip-flop flips on every edge: 0, 1, 0, 1… The output changes half as often as the clock — that is a divide-by-2. A chain of four is a divide-by-16, and all four outputs together are a binary number that grows by 1 with every edge.

2.4. Building

The same project as in lesson 1: the library has the gates and the chips 74HC00–74HC32.

Step 1. Chip NAND3 — NAND with 3 inputs from 6 transistors

If NAND3 is already in the library (from "A Watch and a Game" — there it is made of gates; this one is made of transistors, as in a real chip), skip this step.

As inside a CMOS chip: three pmos in parallel from VCC to the output, three nmos in a chain from the output to GND. The output is 0 only when all three inputs are 1. Transistor: gate, drain, source.

Ctrl+G → name NAND3. Legs: inputs A, B, C; outputs Y.

Step 2. Chip 74HC74 — 2 × D flip-flop with set and reset

Package pins from the datasheet: 1 1RD, 2 1D, 3 1CP, 4 1SD, 5 1Q, 6 1QN, 8 2QN, 9 2Q, 10 2SD, 11 2CP, 12 2D, 13 2RD; 7 — GND, 14 — VCC. SD (set) and RD (reset) are active 0 (in the datasheet they have a bar); QN is the inverted output Q̄. Inside is the classic 7474 circuit: six 3-input NANDs per flip-flop.

Ctrl+G → name 74HC74. Legs: inputs 1RD, 1D, 1CP, 1SD, 2SD, 2CP, 2D, 2RD; outputs 1Q, 1QN, 2QN, 2Q.

Step 3. Clock and reset button

Clock — click the body up to 2Hz. The Reset button is CLR.

Step 4. Reset — through a 74HC04

The 74HC74 reset acts on a zero, and the button gives a one — so we invert it. This is a new 74HC04 from lesson 1: one inverter is used, the inputs of the other five go to GND.

Step 5. Four ÷2 stages

Each flip-flop: D = its own QN — it flips on every edge, that is, divides the frequency by 2. The next one is clocked from the previous QN: when the previous falls from 1 to 0, QN rises — an edge. Two 74HC74 — four stages: Q0 ÷2, Q1 ÷4, Q2 ÷8, Q3 ÷16. SD goes to VCC (no set needed), RD is the common reset nCLR.

Step 6. Lamps and display

Five lamps: CLK and the four stages. Display (bus) ⚙: width 4, DEC, bus Q — shows Q3 Q2 Q1 Q0 as a number.

2.5. Check

1. Clock — 2Hz. Press Reset: all four Q lamps go out, the display shows 0.
2. Watch the lamps: Q0 blinks half as often as CLK, Q1 half as often as Q0, Q2 and Q3 even slower.
3. The display counts 0, 1, 2 … 15, 0 — one per CLK edge: four dividers together are a binary counter.
4. Reset in the middle of counting — at once 0, without waiting for an edge: RD is asynchronous.

Lesson 2 paste (Cmd+I)

On top of lesson 1. If NAND3 is already in the library (from "A Watch and a Game"), the editor will ask which one to keep: both work the same, this one is made of transistors.

# Lesson 2 — 74HC74: two D flip-flops in a package; a ÷2 ÷4 ÷8 ÷16 divider on two 74HC74.# Paste: Cmd+I on top of lesson 1. chip NAND3 {  portIn(A)  portIn(B)  portIn(C)  portOut(Y)  pmos(A, Y, VCC)  pmos(B, Y, VCC)  pmos(C, Y, VCC)  nmos(A, Y, m1)  nmos(B, m1, m2)  nmos(C, m2, GND)} chip 74HC74 {  portIn(1RD)  portIn(1D)  portIn(1CP)  portIn(1SD)  portIn(2SD)  portIn(2CP)  portIn(2D)  portIn(2RD)  portOut(1Q)  portOut(1QN)  portOut(2QN)  portOut(2Q)  NAND3(A=1SD, B=1n4, C=1n2, Y=1n1)  NAND3(A=1n1, B=1RD, C=1CP, Y=1n2)  NAND3(A=1n2, B=1CP, C=1n4, Y=1n3)  NAND3(A=1n3, B=1RD, C=1D, Y=1n4)  NAND3(A=1SD, B=1n2, C=1QN, Y=1Q)  NAND3(A=1Q, B=1n3, C=1RD, Y=1QN)  NAND3(A=2SD, B=2n4, C=2n2, Y=2n1)  NAND3(A=2n1, B=2RD, C=2CP, Y=2n2)  NAND3(A=2n2, B=2CP, C=2n4, Y=2n3)  NAND3(A=2n3, B=2RD, C=2D, Y=2n4)  NAND3(A=2SD, B=2n2, C=2QN, Y=2Q)  NAND3(A=2Q, B=2n3, C=2RD, Y=2QN)} clock(CLK)button{label="Reset"}(CLR)74HC04(1A=CLR, 1Y=nCLR, 2A=GND, 3A=GND, 4A=GND, 5A=GND, 6A=GND)74HC74(1RD=nCLR, 1D=Q0N, 1CP=CLK, 1SD=VCC, 1Q=Q0, 1QN=Q0N, 2QN=Q1N, 2Q=Q1, 2SD=VCC, 2CP=Q0N, 2D=Q1N, 2RD=nCLR)74HC74(1RD=nCLR, 1D=Q2N, 1CP=Q1N, 1SD=VCC, 1Q=Q2, 1QN=Q2N, 2QN=Q3N, 2Q=Q3, 2SD=VCC, 2CP=Q2N, 2D=Q3N, 2RD=nCLR)led(CLK)led(Q0)led(Q1)led(Q2)led(Q3)display{bits=4, base="DEC", busSource="Q"}()