Lesson 1. The ALU and register A: a calculator on switches

After this lesson you will have the heart of the card's processor: you choose an operation and a number with switches, press a button — and register A adds, subtracts, compares. It is a calculator, only its operations are processor commands.

1.1. The idea: one action per clock

In one clock the card's processor does one action: A ← A (operation) B.

• A is the accumulator: an 8-bit register where the result lives;
• B is a number: from the switches for now, later from the program or the memory;
• the operation is a 4-bit code: the same one that will later be in the program word.

The clock is the CLK button: press it — one operation is done, A remembers the result.

1.2. The idea: one adder for four operations

Addition, addition with carry, subtraction and comparison are all done by one adder of eight FAs:

• subtraction is addition of the flipped number plus one: A − B = A + NOT B + 1;
• XOR with the sub signal flips the bits of B, and the one comes in as the carry into the lowest bit;
• CMP is a SUB after which A is not written: only the flags remain.

1.3. The idea: flags are the memory of the result

Two flip-flops remember what the result was: Z — "it came out zero", C — "there was a carry out of the top bit" (for subtraction C = 1 means "there was no borrow", A ≥ B). The program will later decide where to go next by the flags.

1.4. Building

A new project. You need the gates NOT, NAND, NOR, AND, OR, XOR:

• already in the library — take them;
• build them from scratch out of transistors — lesson 0;
• straight to the point — paste lesson 0 (Cmd+I, chip definitions only).

Two flags remember what the result was: Z — zero, C — carry out of the top bit.

Step 1. Chip SRLatch — a latch: two NORs cross-coupled

If SRLatch is already in the library (from "The Fractal Machine" or "Transistor Memory"), skip this step.

Ctrl+G → name SRLatch. Pins: inputs R, S; outputs Q, nQ.

Step 2. Chip DLatch — a latch with enable: EN = 1 — Q follows D

If DLatch is already in the library (from "The Fractal Machine" or "Transistor Memory"), skip this step.

Ctrl+G → name DLatch. Pins: inputs D, EN; outputs Q, nQ.

Step 3. Chip DFF — a flip-flop: remembers D at the moment CLK goes 0 → 1

If DFF is already in the library (from "The Fractal Machine"), skip this step.

Ctrl+G → name DFF. Pins: inputs D, CLK; outputs Q, nQ.

Step 4. Chip MUX2 — a choice of two: S = 0 → A, S = 1 → B

If MUX2 is already in the library (from "A Watch and a Game"), skip this step.

Ctrl+G → name MUX2. Pins: inputs A, B, S; outputs Y.

Step 5. Chip RBIT — a register bit: LD = 1 — remember D on the edge, nR = 0 — remember 0

Ctrl+G → name RBIT. Pins: inputs D, LD, nR, CLK; outputs Q.

Step 6. Chip FA — a full adder for one bit

If FA is already in the library (from "How a CPU Counts" or "A Watch and a Game"), skip this step.

Ctrl+G → name FA. Pins: inputs A, B, CI; outputs S, CO.

Step 7. Chip AND4 — AND with 4 inputs

If AND4 is already in the library (from "A Watch and a Game"), skip this step.

Ctrl+G → name AND4. Pins: inputs A, B, C, D; outputs Y.

Step 8. Chip OR4 — OR with 4 inputs

If OR4 is already in the library (from "Your Own CPU…"), skip this step.

Ctrl+G → name OR4. Pins: inputs A, B, C, D; outputs Y.

Step 9. Chip OR8 — OR with 8 inputs

Ctrl+G → name OR8. Pins: inputs A, B, C, D, E, F, G, H; outputs Y.

Step 10. Chip DEC16 — decoder 4 → 16: exactly one wire is lit

If DEC16 is already in the library (from "Your Own CPU…"), skip this step.

Ctrl+G → name DEC16. Pins: inputs I0, I1, I2, I3; outputs Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12, Y13, Y14, Y15.

Step 11. The panel: operation code, number, clock, reset

Four switches ir12–ir15 are the operation code (as it will be in the ROM word), eight bv0–bv7 are the number. The CLK button is the clock: press it — one operation is done. The RST switch is reset: while it is on, pressing CLK puts 0 into A, C, Z.

Step 12. Decoder and control

DEC16 lights the wire of the operation. Then — who writes what: wA — A is written (codes 0–7 except ST); wZ — flag Z (the same ones plus CMP); wC — flag C (additions, subtraction, CMP); sub — subtraction (SUB, CMP).

Step 13. The adder: ADD, ADC, SUB, CMP

Subtraction is addition of the flipped number plus one: A + NOT B + 1. XOR with sub flips the bits, the one comes in as the carry cin. ADC adds the carry of the previous operation (fC).

Step 14. Logic: AND, OR, XOR

Step 15. Choosing the result

A chain of choices: sum → XOR → OR → AND → the number as is (LD). The wire of the operation is lit — its result goes on, the others go past.

Step 16. Register A and flags Z, C

Z means "the result is zero": OR of all 8 bits, inverted. C is the carry out of the top bit (for subtraction: 1 = "no borrow", A ≥ B).

Step 17. Display and lamps

The display shows A (0–255). The lamps are the flags Z and C.

1.5. Checking

Each row: set the switches and press CLK once. In the switch columns the top bit is on the left, 1 means on.

• LD, AND, OR, XOR change only Z; lamp C stays as it was — that is how it should be.
• Codes 9–15 (jumps) do nothing yet: they need the program counter — lesson 2.
• RST is not instant: the reset happens on a CLK press (the reset is synchronous, like everywhere in the card).

If it is not like this:

• A does not change at all — check LD of the RBITs (label wA) and CLK.
• Only the top bits of the sum are wrong — the carry chain: CI of each FA on the label CO of the previous one (c1…c7).
• SUB adds instead of subtracting — sub on the second input of XOR and on cin.

Do not fold into a chip — the ROM, memory and port will be added to this circuit later.

Lesson 1 paste (Cmd+I)

You need the gates NOT, NAND, NOR, AND, OR, XOR (lesson 0 or its paste).

# Lesson 1 — the ALU and register A: a calculator on switches. Needs the gates NOT, NAND, NOR, AND, OR, XOR (lesson 0).# ---------- SRLatch ----------chip SRLatch {  portIn(R)  portIn(S)  portOut(Q)  portOut(nQ)  NOR(R, nQ, Q)  NOR(S, Q, nQ)} # ---------- DLatch ----------chip DLatch {  portIn(D)  portIn(EN)  portOut(Q)  portOut(nQ)  NOT(D, nD)  AND(D, EN, setD)  AND(nD, EN, rstD)  SRLatch(S=setD, R=rstD, Q=Q, nQ=nQ)} # ---------- DFF ----------chip DFF {  portIn(D)  portIn(CLK)  portOut(Q)  portOut(nQ)  NOT(CLK, nCLK)  DLatch(D=D, EN=nCLK, Q=mid)  DLatch(D=mid, EN=CLK, Q=Q, nQ=nQ)} # ---------- MUX2 ----------chip MUX2 {  portIn(A)  portIn(B)  portIn(S)  portOut(Y)  NOT(S, nS)  NAND(A, nS, na)  NAND(B, S, nb)  NAND(na, nb, Y)} # ---------- RBIT ----------chip RBIT {  portIn(D)  portIn(LD)  portIn(nR)  portIn(CLK)  portOut(Q)  MUX2(A=Q, B=D, S=LD, Y=m)  AND(m, nR, d)  DFF(D=d, CLK=CLK, Q=Q)} # ---------- FA ----------chip FA {  portIn(A)  portIn(B)  portIn(CI)  portOut(S)  portOut(CO)  XOR(A, B, p)  XOR(p, CI, S)  AND(A, B, g)  AND(p, CI, pc)  OR(g, pc, CO)} # ---------- AND4 ----------chip AND4 {  portIn(A)  portIn(B)  portIn(C)  portIn(D)  portOut(Y)  AND(A, B, ab)  AND(ab, C, abc)  AND(abc, D, Y)} # ---------- OR4 ----------chip OR4 {  portIn(A)  portIn(B)  portIn(C)  portIn(D)  portOut(Y)  OR(A, B, ab)  OR(C, D, cd)  OR(ab, cd, Y)} # ---------- OR8 ----------chip OR8 {  portIn(A)  portIn(B)  portIn(C)  portIn(D)  portIn(E)  portIn(F)  portIn(G)  portIn(H)  portOut(Y)  OR4(A=A, B=B, C=C, D=D, Y=lo)  OR4(A=E, B=F, C=G, D=H, Y=hi)  OR(lo, hi, Y)} # ---------- DEC16 ----------chip DEC16 {  portIn(I0)  portIn(I1)  portIn(I2)  portIn(I3)  portOut(Y0)  portOut(Y1)  portOut(Y2)  portOut(Y3)  portOut(Y4)  portOut(Y5)  portOut(Y6)  portOut(Y7)  portOut(Y8)  portOut(Y9)  portOut(Y10)  portOut(Y11)  portOut(Y12)  portOut(Y13)  portOut(Y14)  portOut(Y15)  NOT(I0, n0)  NOT(I1, n1)  NOT(I2, n2)  NOT(I3, n3)  AND4(n3, n2, n1, n0, Y0)  AND4(n3, n2, n1, I0, Y1)  AND4(n3, n2, I1, n0, Y2)  AND4(n3, n2, I1, I0, Y3)  AND4(n3, I2, n1, n0, Y4)  AND4(n3, I2, n1, I0, Y5)  AND4(n3, I2, I1, n0, Y6)  AND4(n3, I2, I1, I0, Y7)  AND4(I3, n2, n1, n0, Y8)  AND4(I3, n2, n1, I0, Y9)  AND4(I3, n2, I1, n0, Y10)  AND4(I3, n2, I1, I0, Y11)  AND4(I3, I2, n1, n0, Y12)  AND4(I3, I2, n1, I0, Y13)  AND4(I3, I2, I1, n0, Y14)  AND4(I3, I2, I1, I0, Y15)} power(Out=VCC)ground(Out=GND)input(Out=ir12)input(Out=ir13)input(Out=ir14)input(Out=ir15)input(Out=bv0)input(Out=bv1)input(Out=bv2)input(Out=bv3)input(Out=bv4)input(Out=bv5)input(Out=bv6)input(Out=bv7)button(Out=CLK)input(Out=RST)NOT(RST, nR) DEC16(I0=ir12, I1=ir13, I2=ir14, I3=ir15, Y0=oLD, Y1=oST, Y2=oADD, Y3=oADC, Y4=oSUB, Y5=oAND, Y6=oOR, Y7=oXOR, Y8=oCMP, Y9=oJMP, Y10=oJZ, Y11=oJNZ, Y12=oJC, Y13=oJNC, Y14=oCALL, Y15=oRET)NOR(ir15, oST, wA)OR(wA, oCMP, wZ)OR4(A=oADD, B=oADC, C=oSUB, D=oCMP, Y=wC)OR(oSUB, oCMP, sub) XOR(bv0, sub, bx0)XOR(bv1, sub, bx1)XOR(bv2, sub, bx2)XOR(bv3, sub, bx3)XOR(bv4, sub, bx4)XOR(bv5, sub, bx5)XOR(bv6, sub, bx6)XOR(bv7, sub, bx7)AND(oADC, fC, adcC)OR(sub, adcC, cin)FA(A=acc0, B=bx0, CI=cin, S=sm0, CO=c1)FA(A=acc1, B=bx1, CI=c1, S=sm1, CO=c2)FA(A=acc2, B=bx2, CI=c2, S=sm2, CO=c3)FA(A=acc3, B=bx3, CI=c3, S=sm3, CO=c4)FA(A=acc4, B=bx4, CI=c4, S=sm4, CO=c5)FA(A=acc5, B=bx5, CI=c5, S=sm5, CO=c6)FA(A=acc6, B=bx6, CI=c6, S=sm6, CO=c7)FA(A=acc7, B=bx7, CI=c7, S=sm7, CO=cout) AND(acc0, bv0, la0)AND(acc1, bv1, la1)AND(acc2, bv2, la2)AND(acc3, bv3, la3)AND(acc4, bv4, la4)AND(acc5, bv5, la5)AND(acc6, bv6, la6)AND(acc7, bv7, la7)OR(acc0, bv0, lo0)OR(acc1, bv1, lo1)OR(acc2, bv2, lo2)OR(acc3, bv3, lo3)OR(acc4, bv4, lo4)OR(acc5, bv5, lo5)OR(acc6, bv6, lo6)OR(acc7, bv7, lo7)XOR(acc0, bv0, lx0)XOR(acc1, bv1, lx1)XOR(acc2, bv2, lx2)XOR(acc3, bv3, lx3)XOR(acc4, bv4, lx4)XOR(acc5, bv5, lx5)XOR(acc6, bv6, lx6)XOR(acc7, bv7, lx7) MUX2(A=sm0, B=lx0, S=oXOR, Y=r1_0)MUX2(A=sm1, B=lx1, S=oXOR, Y=r1_1)MUX2(A=sm2, B=lx2, S=oXOR, Y=r1_2)MUX2(A=sm3, B=lx3, S=oXOR, Y=r1_3)MUX2(A=sm4, B=lx4, S=oXOR, Y=r1_4)MUX2(A=sm5, B=lx5, S=oXOR, Y=r1_5)MUX2(A=sm6, B=lx6, S=oXOR, Y=r1_6)MUX2(A=sm7, B=lx7, S=oXOR, Y=r1_7)MUX2(A=r1_0, B=lo0, S=oOR, Y=r2_0)MUX2(A=r1_1, B=lo1, S=oOR, Y=r2_1)MUX2(A=r1_2, B=lo2, S=oOR, Y=r2_2)MUX2(A=r1_3, B=lo3, S=oOR, Y=r2_3)MUX2(A=r1_4, B=lo4, S=oOR, Y=r2_4)MUX2(A=r1_5, B=lo5, S=oOR, Y=r2_5)MUX2(A=r1_6, B=lo6, S=oOR, Y=r2_6)MUX2(A=r1_7, B=lo7, S=oOR, Y=r2_7)MUX2(A=r2_0, B=la0, S=oAND, Y=r3_0)MUX2(A=r2_1, B=la1, S=oAND, Y=r3_1)MUX2(A=r2_2, B=la2, S=oAND, Y=r3_2)MUX2(A=r2_3, B=la3, S=oAND, Y=r3_3)MUX2(A=r2_4, B=la4, S=oAND, Y=r3_4)MUX2(A=r2_5, B=la5, S=oAND, Y=r3_5)MUX2(A=r2_6, B=la6, S=oAND, Y=r3_6)MUX2(A=r2_7, B=la7, S=oAND, Y=r3_7)MUX2(A=r3_0, B=bv0, S=oLD, Y=res0)MUX2(A=r3_1, B=bv1, S=oLD, Y=res1)MUX2(A=r3_2, B=bv2, S=oLD, Y=res2)MUX2(A=r3_3, B=bv3, S=oLD, Y=res3)MUX2(A=r3_4, B=bv4, S=oLD, Y=res4)MUX2(A=r3_5, B=bv5, S=oLD, Y=res5)MUX2(A=r3_6, B=bv6, S=oLD, Y=res6)MUX2(A=r3_7, B=bv7, S=oLD, Y=res7) RBIT(D=res0, LD=wA, nR=nR, CLK=CLK, Q=acc0)RBIT(D=res1, LD=wA, nR=nR, CLK=CLK, Q=acc1)RBIT(D=res2, LD=wA, nR=nR, CLK=CLK, Q=acc2)RBIT(D=res3, LD=wA, nR=nR, CLK=CLK, Q=acc3)RBIT(D=res4, LD=wA, nR=nR, CLK=CLK, Q=acc4)RBIT(D=res5, LD=wA, nR=nR, CLK=CLK, Q=acc5)RBIT(D=res6, LD=wA, nR=nR, CLK=CLK, Q=acc6)RBIT(D=res7, LD=wA, nR=nR, CLK=CLK, Q=acc7)OR8(A=res0, B=res1, C=res2, D=res3, E=res4, F=res5, G=res6, H=res7, Y=nz)NOT(nz, zr)RBIT(D=zr, LD=wZ, nR=nR, CLK=CLK, Q=fZ)RBIT(D=cout, LD=wC, nR=nR, CLK=CLK, Q=fC) display{bits=8, base="DEC", busSource="acc"}()led(fZ)led(fC)