Lesson 3. RAM from latches: a light through memory

After this lesson the processor gets memory — 8 cells of 8 bits made of transistors. And you can see right away why it is needed: the light runs on a program of five commands, because the processor can add a memory cell to A.

3.1. The idea: the address is in the command

ST 3 puts A into cell 3, LD 3 takes it out, ADD 3 adds the cell to A. The cell number is in the low bits of the command, like the number of LD #5, only ir11 = 0. The addresses are divided into areas:

• 0–7 — RAM;
• 16–23 — permanent memory (the card's personal data, lesson 6);
• 24 — the PIN try counter (lesson 6), 28–29 — the data wire (lesson 5).

The row inside an area is chosen by the decoder DEC8 — one for the RAM and the permanent memory.

3.2. The idea: a latch writes while it is open

A RAM cell is 8 latches. A latch remembers while it is open, so it may be opened only when the address and A have settled. The clock is split into two halves: CLK = 1 — read, CLK = 0 — write. The write window weRAM is open in the second half and is closed by the CLK edge itself — before PC changes.

3.3. The idea: memory at power-on is garbage

At power-on the latches remember nothing: in Real they "float" (orange). So the program first writes a cell and only then reads it. Real computers are the same: memory has to be filled after power-on.

3.4. Building

The same project as in lesson 2.

We build the RAM from latches: a row of 8 latches for each cell. Reading is always on (the selected row gives what it holds), writing only by the ST command and only in the second half of the clock.

Step 1. Chip AND3 — AND with 3 inputs

If AND3 is already in the library (from "A Watch and a Game"), skip this step.

Ctrl+G → name AND3. Pins: inputs A, B, C; outputs Y.

Step 2. Chip DEC8 — decoder 3 → 8: exactly one wire is lit

Ctrl+G → name DEC8. Pins: inputs I0, I1, I2; outputs Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7.

Step 3. Chip WORD8 — a RAM row: 8 latches, write by W, read by R

Ctrl+G → name WORD8. Pins: inputs D0, D1, D2, D3, D4, D5, D6, D7, W, R; outputs O0, O1, O2, O3, O4, O5, O6, O7.

Step 4. What is selected: area and row

The cell address is the low bits of the command. ir4 = 0 — RAM (addresses 0–7); ir4 = 1 — the rest: 16–23 the permanent memory (selP), 24 the try counter (selTRY), 28–29 the IO wire (selIO). The row inside the area is chosen by DEC8 from ir0–ir2 — one decoder for the RAM and the permanent memory.

Step 5. The write window and the rows

A latch writes while it is open. So ST opens the row only in the second half of the clock (CLK = 0, nCLK = 1): by then the address and A have long settled, and the window is closed by the CLK edge itself — before PC changes. Two phases of one clock: CLK = 1 — read, CLK = 0 — write to memory. rr is the row for reading, rw for writing.

Step 6. Eight RAM rows

Each row is 8 latches. D0–D7 come from A (what to write), O is what is read: a row that is not selected gives zeros there.

Step 7. Reading the RAM

For each bit — OR of all 8 rows: only the selected one is lit, the others give 0.

Step 8. Room for the permanent memory

The card's personal data — account number, PIN, key — will live in a matrix, like the ROM of the "Character Generator": rows pr, columns pb, a resistor holds the column at 1, a row transistor pulls it to 0, NOT flips it. We will place the transistors (the data itself) in lesson 6; for now the matrix is empty: everything reads as 0.

Step 9. Everything meets in din

Whatever is read — RAM, permanent memory, try counter or the IO wire — meets by OR in din0–din7, and from there goes to the number MUX2s of lesson 2. The try counter (try0, try1) and the IO wire will appear in lessons 5–6: for now their labels are empty, and an AND with an area that is not selected gives 0 anyway.

Step 10. The program in the ROM

⚙ on ROM → button ⬆ → file 03-shift.rom.json. Only 5 commands:

; Lesson 3 — a light shifted through memory: A + A shifts the bits left, but the second addend must come from somewhere —; the command adds A to a CELL. We put A into cell 0 and add that same cell.start:  LD #1loop:   ST 0             ; cell 0 ← A        ADD 0            ; A ← A + cell 0 = A + A: the light steps left        JNC loop         ; until the one falls out of the 8 bits        JMP start        ; 128 + 128 = 256 → A = 0, C = 1 — from the start

3.5. Checking

Reset (RST for one or two clocks) — and the clock steps by itself. The light runs left one lamp per 3 clocks (ST, ADD, JNC), after 128 it goes dark for 3 clocks (A = 0, C = 1) and starts again.

• A changes only on ADD and LD; ST and the jumps do not touch A — the lamps stand still.
• C lights up when 128 + 128 falls out of 8 bits, and goes off on the next ADD (LD, ST and the jumps do not touch C).
• The main thing: the command ADD 0 adds A to a memory cell. Without RAM (lesson 2) the shift had to be written with eight LDs.

If it is not like this:

• A does not double after ADD 0 — check the write window: AND3 → weRAM with oST, selRAM, nCLK; rows rw, rr.
• It doubles, but the wrong bit — WORD8: D0–D7 on acc0–acc7, O of a row is m<row>_<bit>; OR8 of bit k has inputs m0_k…m7_k.
• All lamps are lit instead of one light — din does not come from the RAM: check OR in din2–din7, OR3 in din1, OR4 in din0.
• Orange (Z) labels try0, try1, IO — that is how it should be: their sources appear in lessons 5–6.

Do not fold into a chip.

Lesson 3 paste (Cmd+I)

On top of lesson 2.

# Lesson 3 — RAM from latches, room for the permanent memory. On top of lesson 2; then load 03-shift.rom.json into ROM.# ---------- AND3 ----------chip AND3 {  portIn(A)  portIn(B)  portIn(C)  portOut(Y)  AND(A, B, ab)  AND(ab, C, Y)} # ---------- DEC8 ----------chip DEC8 {  portIn(I0)  portIn(I1)  portIn(I2)  portOut(Y0)  portOut(Y1)  portOut(Y2)  portOut(Y3)  portOut(Y4)  portOut(Y5)  portOut(Y6)  portOut(Y7)  NOT(I0, n0)  NOT(I1, n1)  NOT(I2, n2)  AND3(A=n2, B=n1, C=n0, Y=Y0)  AND3(A=n2, B=n1, C=I0, Y=Y1)  AND3(A=n2, B=I1, C=n0, Y=Y2)  AND3(A=n2, B=I1, C=I0, Y=Y3)  AND3(A=I2, B=n1, C=n0, Y=Y4)  AND3(A=I2, B=n1, C=I0, Y=Y5)  AND3(A=I2, B=I1, C=n0, Y=Y6)  AND3(A=I2, B=I1, C=I0, Y=Y7)} # ---------- WORD8 ----------chip WORD8 {  portIn(D0)  portIn(D1)  portIn(D2)  portIn(D3)  portIn(D4)  portIn(D5)  portIn(D6)  portIn(D7)  portIn(W)  portIn(R)  portOut(O0)  portOut(O1)  portOut(O2)  portOut(O3)  portOut(O4)  portOut(O5)  portOut(O6)  portOut(O7)  DLatch(D=D0, EN=W, Q=q0)  DLatch(D=D1, EN=W, Q=q1)  DLatch(D=D2, EN=W, Q=q2)  DLatch(D=D3, EN=W, Q=q3)  DLatch(D=D4, EN=W, Q=q4)  DLatch(D=D5, EN=W, Q=q5)  DLatch(D=D6, EN=W, Q=q6)  DLatch(D=D7, EN=W, Q=q7)  AND(q0, R, O0)  AND(q1, R, O1)  AND(q2, R, O2)  AND(q3, R, O3)  AND(q4, R, O4)  AND(q5, R, O5)  AND(q6, R, O6)  AND(q7, R, O7)} NOT(ir4, selRAM)NOT(ir3, nir3)NOT(ir2, nir2)AND(ir4, nir3, selP)AND3(A=ir4, B=ir3, C=nir2, Y=selTRY)AND3(A=ir4, B=ir3, C=ir2, Y=selIO)DEC8(I0=ir0, I1=ir1, I2=ir2, Y0=row0, Y1=row1, Y2=row2, Y3=row3, Y4=row4, Y5=row5, Y6=row6, Y7=row7) NOT(CLK, nCLK)AND3(A=oST, B=selRAM, C=nCLK, Y=weRAM)AND(row0, selRAM, rr0)AND(row1, selRAM, rr1)AND(row2, selRAM, rr2)AND(row3, selRAM, rr3)AND(row4, selRAM, rr4)AND(row5, selRAM, rr5)AND(row6, selRAM, rr6)AND(row7, selRAM, rr7)AND(row0, weRAM, rw0)AND(row1, weRAM, rw1)AND(row2, weRAM, rw2)AND(row3, weRAM, rw3)AND(row4, weRAM, rw4)AND(row5, weRAM, rw5)AND(row6, weRAM, rw6)AND(row7, weRAM, rw7) WORD8(D0=acc0, D1=acc1, D2=acc2, D3=acc3, D4=acc4, D5=acc5, D6=acc6, D7=acc7, W=rw0, R=rr0, O0=m0_0, O1=m0_1, O2=m0_2, O3=m0_3, O4=m0_4, O5=m0_5, O6=m0_6, O7=m0_7)WORD8(D0=acc0, D1=acc1, D2=acc2, D3=acc3, D4=acc4, D5=acc5, D6=acc6, D7=acc7, W=rw1, R=rr1, O0=m1_0, O1=m1_1, O2=m1_2, O3=m1_3, O4=m1_4, O5=m1_5, O6=m1_6, O7=m1_7)WORD8(D0=acc0, D1=acc1, D2=acc2, D3=acc3, D4=acc4, D5=acc5, D6=acc6, D7=acc7, W=rw2, R=rr2, O0=m2_0, O1=m2_1, O2=m2_2, O3=m2_3, O4=m2_4, O5=m2_5, O6=m2_6, O7=m2_7)WORD8(D0=acc0, D1=acc1, D2=acc2, D3=acc3, D4=acc4, D5=acc5, D6=acc6, D7=acc7, W=rw3, R=rr3, O0=m3_0, O1=m3_1, O2=m3_2, O3=m3_3, O4=m3_4, O5=m3_5, O6=m3_6, O7=m3_7)WORD8(D0=acc0, D1=acc1, D2=acc2, D3=acc3, D4=acc4, D5=acc5, D6=acc6, D7=acc7, W=rw4, R=rr4, O0=m4_0, O1=m4_1, O2=m4_2, O3=m4_3, O4=m4_4, O5=m4_5, O6=m4_6, O7=m4_7)WORD8(D0=acc0, D1=acc1, D2=acc2, D3=acc3, D4=acc4, D5=acc5, D6=acc6, D7=acc7, W=rw5, R=rr5, O0=m5_0, O1=m5_1, O2=m5_2, O3=m5_3, O4=m5_4, O5=m5_5, O6=m5_6, O7=m5_7)WORD8(D0=acc0, D1=acc1, D2=acc2, D3=acc3, D4=acc4, D5=acc5, D6=acc6, D7=acc7, W=rw6, R=rr6, O0=m6_0, O1=m6_1, O2=m6_2, O3=m6_3, O4=m6_4, O5=m6_5, O6=m6_6, O7=m6_7)WORD8(D0=acc0, D1=acc1, D2=acc2, D3=acc3, D4=acc4, D5=acc5, D6=acc6, D7=acc7, W=rw7, R=rr7, O0=m7_0, O1=m7_1, O2=m7_2, O3=m7_3, O4=m7_4, O5=m7_5, O6=m7_6, O7=m7_7) OR8(A=m0_0, B=m1_0, C=m2_0, D=m3_0, E=m4_0, F=m5_0, G=m6_0, H=m7_0, Y=ram0)OR8(A=m0_1, B=m1_1, C=m2_1, D=m3_1, E=m4_1, F=m5_1, G=m6_1, H=m7_1, Y=ram1)OR8(A=m0_2, B=m1_2, C=m2_2, D=m3_2, E=m4_2, F=m5_2, G=m6_2, H=m7_2, Y=ram2)OR8(A=m0_3, B=m1_3, C=m2_3, D=m3_3, E=m4_3, F=m5_3, G=m6_3, H=m7_3, Y=ram3)OR8(A=m0_4, B=m1_4, C=m2_4, D=m3_4, E=m4_4, F=m5_4, G=m6_4, H=m7_4, Y=ram4)OR8(A=m0_5, B=m1_5, C=m2_5, D=m3_5, E=m4_5, F=m5_5, G=m6_5, H=m7_5, Y=ram5)OR8(A=m0_6, B=m1_6, C=m2_6, D=m3_6, E=m4_6, F=m5_6, G=m6_6, H=m7_6, Y=ram6)OR8(A=m0_7, B=m1_7, C=m2_7, D=m3_7, E=m4_7, F=m5_7, G=m6_7, H=m7_7, Y=ram7) AND(row0, selP, pr0)AND(row1, selP, pr1)AND(row2, selP, pr2)AND(row3, selP, pr3)AND(row4, selP, pr4)AND(row5, selP, pr5)AND(row6, selP, pr6)resistor(VCC, pb0)resistor(VCC, pb1)resistor(VCC, pb2)resistor(VCC, pb3)resistor(VCC, pb4)resistor(VCC, pb5)resistor(VCC, pb6)resistor(VCC, pb7)NOT(pb0, pq0)NOT(pb1, pq1)NOT(pb2, pq2)NOT(pb3, pq3)NOT(pb4, pq4)NOT(pb5, pq5)NOT(pb6, pq6)NOT(pb7, pq7) AND(try0, selTRY, t0)AND(try1, selTRY, t1)AND(IO, selIO, io0)OR4(A=ram0, B=pq0, C=t0, D=io0, Y=din0)OR3(A=ram1, B=pq1, C=t1, Y=din1)OR(ram2, pq2, din2)OR(ram3, pq3, din3)OR(ram4, pq4, din4)OR(ram5, pq5, din5)OR(ram6, pq6, din6)OR(ram7, pq7, din7)