Kits
›
The Payment Card
RU
EN
ES
Contents
Introduction
History: from cardboard to a computer
Lesson 0. Gates from transistors: for those who start from scratch
0.1. The idea: a transistor is a switch
0.2. Building
0.3. Check
Lesson 0 paste (Cmd+I)
Lesson 1. The ALU and register A: a calculator on switches
1.1. The idea: one action per clock
1.2. The idea: one adder for four operations
1.3. The idea: flags are the memory of the result
1.4. Building
1.5. Checking
Lesson 1 paste (Cmd+I)
Lesson 2. The program counter and ROM: lights by the program
2.1. The idea: a program is a list of commands
2.2. The idea: jumps and a subroutine
2.3. Building
2.4. Checking
Lesson 2 paste (Cmd+I)
Lesson 3. RAM from latches: a light through memory
3.1. The idea: the address is in the command
3.2. The idea: a latch writes while it is open
3.3. The idea: memory at power-on is garbage
3.4. Building
3.5. Checking
Lesson 3 paste (Cmd+I)
Lesson 4. Loops and conditions: multiplication by repeated addition
4.1. The idea: a counter down to zero
4.2. The program
4.3. Checking
Lesson 5. The IO wire and the card tester: echo
5.1. The idea: one wire for two
5.2. The idea: a byte bit by bit
5.3. The idea: the "exchange — wait" lamp
5.4. Building
5.5. Checking
Lesson 5 paste (Cmd+I)
Lesson 6. Personal data and the try counter: the card checks the PIN
6.1. The idea: the identity is in transistors
6.2. The idea: tries that are not erased
6.3. Building
6.4. Checking
Lesson 6 paste (Cmd+I)
Lesson 7. The card program: challenge-response
7.1. The idea: a secret that never leaves
7.2. The idea: a long answer in two commands
7.3. The program
7.4. Checking
Lesson 8. The card — into a chip with 8 legs
8.1. The idea: a card is what is inside
8.2. The idea: two cards — one program
8.3. Building
8.4. Checking
Lesson 8 paste (Cmd+I)
Summary
All the parts
Instructions in pictures
Lesson 3 in pictures
← Back to the lesson: Lesson 3. RAM from latches: a light through memory
3
RAM from latches
8 memory cells and room for the personal data
kh
HT-01
0
1
2
3
4
5
6
7
ST 0
A → cell 0
ADD 0
A + cell 0
IN
16×
OUT
17×
AND
37×
0
NOT
15×
0
DLatch
8×
1
OR8
8×
1
8×
OR4
1×
1
OR3
1×
2
OR
6×
0
∞
Ctrl
+
G
AND3
DEC8
WORD8
© 2026 Daniil Khanin · khanin.info · HT-01
52
AND3
DEC8
1
IN
3×
OUT
1×
AND
2×
0
6×
A
B
C
Y
AND
I0
A
I1
B
O0
ab
AND
I0
ab
I1
C
O0
Y
2
Ctrl
+
G
Library
…
Chip N
2×
Library
…
AND3
Enter
AND3
A
B
C
Y
3
IN
3×
OUT
8×
I0
I1
I2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
© 2026 Daniil Khanin · khanin.info · HT-01
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DEC8 …
4
NOT
3×
0
6×
NOT
I0
I0
O0
n0
NOT
I0
I1
O0
n1
NOT
I0
I2
O0
n2
5
AND3
3×
12×
AND3
A
n2
B
n1
C
n0
Y
Y0
AND3
A
n2
B
n1
C
I0
Y
Y1
AND3
A
n2
B
I1
C
n0
Y
Y2
© 2026 Daniil Khanin · khanin.info · HT-01
54
DEC8 …
6
AND3
3×
12×
AND3
A
n2
B
I1
C
I0
Y
Y3
AND3
A
I2
B
n1
C
n0
Y
Y4
AND3
A
I2
B
n1
C
I0
Y
Y5
7
AND3
2×
8×
AND3
A
I2
B
I1
C
n0
Y
Y6
AND3
A
I2
B
I1
C
I0
Y
Y7
8
Ctrl
+
G
Library
…
Chip N
2×
Library
…
DEC8
Enter
DEC8
I0
I1
I2
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
© 2026 Daniil Khanin · khanin.info · HT-01
55
WORD8
9
IN
10×
OUT
8×
D0
D1
D2
D3
D4
D5
D6
D7
W
R
O0
O1
O2
O3
O4
O5
O6
O7
10
DLatch
3×
1
9×
DLatch
D
D0
EN
W
Q
q0
nQ
DLatch
D
D1
EN
W
Q
q1
nQ
DLatch
D
D2
EN
W
Q
q2
nQ
11
DLatch
3×
1
9×
DLatch
D
D3
EN
W
Q
q3
nQ
DLatch
D
D4
EN
W
Q
q4
nQ
DLatch
D
D5
EN
W
Q
q5
nQ
© 2026 Daniil Khanin · khanin.info · HT-01
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WORD8 …
12
DLatch
2×
1
AND
1×
0
9×
DLatch
D
D6
EN
W
Q
q6
nQ
DLatch
D
D7
EN
W
Q
q7
nQ
AND
I0
q0
I1
R
O0
O0
13
AND
3×
0
9×
AND
I0
q1
I1
R
O0
O1
AND
I0
q2
I1
R
O0
O2
AND
I0
q3
I1
R
O0
O3
14
AND
3×
0
9×
AND
I0
q4
I1
R
O0
O4
AND
I0
q5
I1
R
O0
O5
AND
I0
q6
I1
R
O0
O6
© 2026 Daniil Khanin · khanin.info · HT-01
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WORD8 …
CANVAS
15
AND
1×
0
3×
AND
I0
q7
I1
R
O0
O7
16
Ctrl
+
G
Library
…
Chip N
2×
Library
…
WORD8
Enter
WORD8
D0
D1
D2
D3
D4
D5
D6
D7
W
R
O0
O1
O2
O3
O4
O5
O6
O7
17
NOT
3×
0
6×
NOT
I0
ir4
O0
selRAM
NOT
I0
ir3
O0
nir3
NOT
I0
ir2
O0
nir2
© 2026 Daniil Khanin · khanin.info · HT-01
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CANVAS …
18
AND
1×
0
AND3
2×
11×
AND
I0
ir4
I1
nir3
O0
selP
AND3
A
ir4
B
ir3
C
nir2
Y
selTRY
AND3
A
ir4
B
ir3
C
ir2
Y
selIO
19
DEC8
1×
11×
DEC8
I0
ir0
I1
ir1
I2
ir2
Y0
row0
Y1
row1
Y2
row2
Y3
row3
Y4
row4
Y5
row5
Y6
row6
Y7
row7
20
NOT
1×
0
AND3
1×
AND
1×
0
9×
NOT
I0
CLK
O0
nCLK
AND3
A
oST
B
selRAM
C
nCLK
Y
weRAM
AND
I0
row0
I1
selRAM
O0
rr0
© 2026 Daniil Khanin · khanin.info · HT-01
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CANVAS …
21
AND
3×
0
9×
AND
I0
row1
I1
selRAM
O0
rr1
AND
I0
row2
I1
selRAM
O0
rr2
AND
I0
row3
I1
selRAM
O0
rr3
22
AND
3×
0
9×
AND
I0
row4
I1
selRAM
O0
rr4
AND
I0
row5
I1
selRAM
O0
rr5
AND
I0
row6
I1
selRAM
O0
rr6
23
AND
3×
0
9×
AND
I0
row7
I1
selRAM
O0
rr7
AND
I0
row0
I1
weRAM
O0
rw0
AND
I0
row1
I1
weRAM
O0
rw1
© 2026 Daniil Khanin · khanin.info · HT-01
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CANVAS …
24
AND
3×
0
9×
AND
I0
row2
I1
weRAM
O0
rw2
AND
I0
row3
I1
weRAM
O0
rw3
AND
I0
row4
I1
weRAM
O0
rw4
25
AND
3×
0
9×
AND
I0
row5
I1
weRAM
O0
rw5
AND
I0
row6
I1
weRAM
O0
rw6
AND
I0
row7
I1
weRAM
O0
rw7
26
WORD8
1×
18×
WORD8
D0
acc0
D1
acc1
D2
acc2
D3
acc3
D4
acc4
D5
acc5
D6
acc6
D7
acc7
W
rw0
R
rr0
O0
m0_0
O1
m0_1
O2
m0_2
O3
m0_3
O4
m0_4
O5
m0_5
O6
m0_6
O7
m0_7
© 2026 Daniil Khanin · khanin.info · HT-01
61
CANVAS …
27
WORD8
1×
18×
WORD8
D0
acc0
D1
acc1
D2
acc2
D3
acc3
D4
acc4
D5
acc5
D6
acc6
D7
acc7
W
rw1
R
rr1
O0
m1_0
O1
m1_1
O2
m1_2
O3
m1_3
O4
m1_4
O5
m1_5
O6
m1_6
O7
m1_7
28
WORD8
1×
18×
WORD8
D0
acc0
D1
acc1
D2
acc2
D3
acc3
D4
acc4
D5
acc5
D6
acc6
D7
acc7
W
rw2
R
rr2
O0
m2_0
O1
m2_1
O2
m2_2
O3
m2_3
O4
m2_4
O5
m2_5
O6
m2_6
O7
m2_7
29
WORD8
1×
18×
WORD8
D0
acc0
D1
acc1
D2
acc2
D3
acc3
D4
acc4
D5
acc5
D6
acc6
D7
acc7
W
rw3
R
rr3
O0
m3_0
O1
m3_1
O2
m3_2
O3
m3_3
O4
m3_4
O5
m3_5
O6
m3_6
O7
m3_7
© 2026 Daniil Khanin · khanin.info · HT-01
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CANVAS …
30
WORD8
1×
18×
WORD8
D0
acc0
D1
acc1
D2
acc2
D3
acc3
D4
acc4
D5
acc5
D6
acc6
D7
acc7
W
rw4
R
rr4
O0
m4_0
O1
m4_1
O2
m4_2
O3
m4_3
O4
m4_4
O5
m4_5
O6
m4_6
O7
m4_7
31
WORD8
1×
18×
WORD8
D0
acc0
D1
acc1
D2
acc2
D3
acc3
D4
acc4
D5
acc5
D6
acc6
D7
acc7
W
rw5
R
rr5
O0
m5_0
O1
m5_1
O2
m5_2
O3
m5_3
O4
m5_4
O5
m5_5
O6
m5_6
O7
m5_7
32
WORD8
1×
18×
WORD8
D0
acc0
D1
acc1
D2
acc2
D3
acc3
D4
acc4
D5
acc5
D6
acc6
D7
acc7
W
rw6
R
rr6
O0
m6_0
O1
m6_1
O2
m6_2
O3
m6_3
O4
m6_4
O5
m6_5
O6
m6_6
O7
m6_7
© 2026 Daniil Khanin · khanin.info · HT-01
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CANVAS …
33
WORD8
1×
18×
WORD8
D0
acc0
D1
acc1
D2
acc2
D3
acc3
D4
acc4
D5
acc5
D6
acc6
D7
acc7
W
rw7
R
rr7
O0
m7_0
O1
m7_1
O2
m7_2
O3
m7_3
O4
m7_4
O5
m7_5
O6
m7_6
O7
m7_7
34
OR8
1×
1
9×
OR8
A
m0_0
B
m1_0
C
m2_0
D
m3_0
E
m4_0
F
m5_0
G
m6_0
H
m7_0
Y
ram0
35
OR8
1×
1
9×
OR8
A
m0_1
B
m1_1
C
m2_1
D
m3_1
E
m4_1
F
m5_1
G
m6_1
H
m7_1
Y
ram1
© 2026 Daniil Khanin · khanin.info · HT-01
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CANVAS …
36
OR8
1×
1
9×
OR8
A
m0_2
B
m1_2
C
m2_2
D
m3_2
E
m4_2
F
m5_2
G
m6_2
H
m7_2
Y
ram2
37
OR8
1×
1
9×
OR8
A
m0_3
B
m1_3
C
m2_3
D
m3_3
E
m4_3
F
m5_3
G
m6_3
H
m7_3
Y
ram3
38
OR8
1×
1
9×
OR8
A
m0_4
B
m1_4
C
m2_4
D
m3_4
E
m4_4
F
m5_4
G
m6_4
H
m7_4
Y
ram4
© 2026 Daniil Khanin · khanin.info · HT-01
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CANVAS …
39
OR8
1×
1
9×
OR8
A
m0_5
B
m1_5
C
m2_5
D
m3_5
E
m4_5
F
m5_5
G
m6_5
H
m7_5
Y
ram5
40
OR8
1×
1
9×
OR8
A
m0_6
B
m1_6
C
m2_6
D
m3_6
E
m4_6
F
m5_6
G
m6_6
H
m7_6
Y
ram6
41
OR8
1×
1
9×
OR8
A
m0_7
B
m1_7
C
m2_7
D
m3_7
E
m4_7
F
m5_7
G
m6_7
H
m7_7
Y
ram7
42
AND
3×
0
9×
AND
I0
row0
I1
selP
O0
pr0
AND
I0
row1
I1
selP
O0
pr1
AND
I0
row2
I1
selP
O0
pr2
© 2026 Daniil Khanin · khanin.info · HT-01
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CANVAS …
43
AND
3×
0
9×
AND
I0
row3
I1
selP
O0
pr3
AND
I0
row4
I1
selP
O0
pr4
AND
I0
row5
I1
selP
O0
pr5
44
AND
1×
0
2×
7×
AND
I0
row6
I1
selP
O0
pr6
VCC
pb0
VCC
pb1
45
3×
6×
VCC
pb2
VCC
pb3
VCC
pb4
© 2026 Daniil Khanin · khanin.info · HT-01
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CANVAS …
46
3×
6×
VCC
pb5
VCC
pb6
VCC
pb7
47
NOT
3×
0
6×
NOT
I0
pb0
O0
pq0
NOT
I0
pb1
O0
pq1
NOT
I0
pb2
O0
pq2
48
NOT
3×
0
6×
NOT
I0
pb3
O0
pq3
NOT
I0
pb4
O0
pq4
NOT
I0
pb5
O0
pq5
49
NOT
2×
0
4×
NOT
I0
pb6
O0
pq6
NOT
I0
pb7
O0
pq7
© 2026 Daniil Khanin · khanin.info · HT-01
68
CANVAS …
50
AND
3×
0
9×
AND
I0
try0
I1
selTRY
O0
t0
AND
I0
try1
I1
selTRY
O0
t1
AND
I0
IO
I1
selIO
O0
io0
51
OR4
1×
1
OR3
1×
2
9×
OR4
A
ram0
B
pq0
C
t0
D
io0
Y
din0
OR3
A
ram1
B
pq1
C
t1
Y
din1
52
OR
3×
0
9×
OR
I0
ram2
I1
pq2
O0
din2
OR
I0
ram3
I1
pq3
O0
din3
OR
I0
ram4
I1
pq4
O0
din4
© 2026 Daniil Khanin · khanin.info · HT-01
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CANVAS …
53
OR
3×
0
9×
OR
I0
ram5
I1
pq5
O0
din5
OR
I0
ram6
I1
pq6
O0
din6
OR
I0
ram7
I1
pq7
O0
din7
54
ROM
256 × 16
Memory
⬆
⬇
0801 0802 0804
0808 0810 0820
0840 0880 E011
03-shift.rom.json
1
2
4
8
128
0
3 × CLK: ST 0 · ADD 0 · JNC
© 2026 Daniil Khanin · khanin.info · HT-01
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← Back to the lesson
Lesson 3. RAM from latches: a light through memory