Lesson 3. 256×4 memory: the same circuit one level up

In pictures

After this lesson you will have RAM256x4 — 256 words of 4 bits, 128 bytes: exactly as much memory as the processor kit's machine has. There are almost no new ideas: sixteen RAM16x4 chips from lesson 2 are put together into a big memory the same way sixteen rows were put together into RAM16x4.

3.1. The idea: the address splits in half

The address is 8 bits: A7 A6 A5 A4 | A3 A2 A1 A0.

  • The low 4 bits go to all 16 blocks at once — in each one they pick a cell inside the block.
  • The high 4 bits → DEC16 lights one wire b0–b15 — which block is working: AND(bN, WE) — writing only into this block; AND(block output, bN) — only its data goes further.
  • An OR of the 16 blocks for each bit — the output is the cell of the selected block.
address00100101A7–A4 = 2A3–A0 = 5DEC16blockto every block: cell 5RAM16x4block 0RAM16x4block 1RAM16x4block 2RAM16x4block 15⋯WE and "let through" —block 2 onlyOR of blocks → Q
256×4 from sixteen 16×4 — the same circuit one level up. The low 4 address bits go to all blocks at once and choose the cell inside a block; the high 4 bits choose the block through DEC16: only it gets WE, only its output passes into the OR.
Inside RAM16x4Inside RAM256x4
DEC16 picks a WORD4 rowDEC16 picks a RAM16x4 block
AND(r, WE) — write only into this rowAND(b, WE) — WE only to this block
AND(q, R) — the row gives out only if selectedAND(Q, b) — the block gives out only if selected
OR of 16 rowsOR of 16 blocks

Example. Address 0010 0101 (hex 25): the high 0010 = 2 — block 2 is working; the low 0101 = 5 — cell 5 in it. Address 0001 0101 (15) — cell 5 too, but of block 1: a different cell.

3.2. The cost

Almost all of the memory is latches: 1,024 bits × 22 transistors. Together with row selection and the OR trees the RAM256x4 chip is 41,840 transistors, seven times more than the whole processor. In REAL such a circuit is slow to compute: after a switch is flipped the display updates in a second or two. In Fast — immediately.

3.3. Building

Step 1. Remove lesson 2's test bench

Lesson 3's test bench uses the same labels mA, mD, mQ. Two parts on one label are a short, so first delete lesson 2's test bench (the chips stay in the Library):

ElementAction
Input, whose output = mA0delete
Input, whose output = mA1delete
Input, whose output = mA2delete
Input, whose output = mA3delete
Input, whose output = mD0delete
Input, whose output = mD1delete
Input, whose output = mD2delete
Input, whose output = mD3delete
Button WE, whose output = mWEdelete
RAM16x4, whose output = mQ0delete
three displays (buses mA, mD, mQ)delete

The VCC/GND power and lesson 1's test bench can stay.

Step 2. The RAM256x4 chip

What we build. Block selection, 16 "write" gates, 16 blocks, 64 "pass" gates and an OR tree.

INPUT PORTS: A0, A1, A2, A3, A4, A5, A6, A7, D0, D1, D2, D3, WE · OUTPUT PORTS: Q0, Q1, Q2, Q3

ElementPinDirectionLabel
DEC16I0inA4
DEC16I1inA5
DEC16I2inA6
DEC16I3inA7
DEC16Y0outb0
DEC16Y1outb1
DEC16Y2outb2
DEC16Y3outb3
DEC16Y4outb4
DEC16Y5outb5
DEC16Y6outb6
DEC16Y7outb7
DEC16Y8outb8
DEC16Y9outb9
DEC16Y10outb10
DEC16Y11outb11
DEC16Y12outb12
DEC16Y13outb13
DEC16Y14outb14
DEC16Y15outb15
ANDI0inb0
ANDI1inWE
ANDO0outw0
ANDI0inb1
ANDI1inWE
ANDO0outw1
ANDI0inb2
ANDI1inWE
ANDO0outw2
ANDI0inb3
ANDI1inWE
ANDO0outw3
ANDI0inb4
ANDI1inWE
ANDO0outw4
ANDI0inb5
ANDI1inWE
ANDO0outw5
ANDI0inb6
ANDI1inWE
ANDO0outw6
ANDI0inb7
ANDI1inWE
ANDO0outw7
ANDI0inb8
ANDI1inWE
ANDO0outw8
ANDI0inb9
ANDI1inWE
ANDO0outw9
ANDI0inb10
ANDI1inWE
ANDO0outw10
ANDI0inb11
ANDI1inWE
ANDO0outw11
ANDI0inb12
ANDI1inWE
ANDO0outw12
ANDI0inb13
ANDI1inWE
ANDO0outw13
ANDI0inb14
ANDI1inWE
ANDO0outw14
ANDI0inb15
ANDI1inWE
ANDO0outw15
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw0
RAM16x4Q0outm0_0
RAM16x4Q1outm0_1
RAM16x4Q2outm0_2
RAM16x4Q3outm0_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw1
RAM16x4Q0outm1_0
RAM16x4Q1outm1_1
RAM16x4Q2outm1_2
RAM16x4Q3outm1_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw2
RAM16x4Q0outm2_0
RAM16x4Q1outm2_1
RAM16x4Q2outm2_2
RAM16x4Q3outm2_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw3
RAM16x4Q0outm3_0
RAM16x4Q1outm3_1
RAM16x4Q2outm3_2
RAM16x4Q3outm3_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw4
RAM16x4Q0outm4_0
RAM16x4Q1outm4_1
RAM16x4Q2outm4_2
RAM16x4Q3outm4_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw5
RAM16x4Q0outm5_0
RAM16x4Q1outm5_1
RAM16x4Q2outm5_2
RAM16x4Q3outm5_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw6
RAM16x4Q0outm6_0
RAM16x4Q1outm6_1
RAM16x4Q2outm6_2
RAM16x4Q3outm6_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw7
RAM16x4Q0outm7_0
RAM16x4Q1outm7_1
RAM16x4Q2outm7_2
RAM16x4Q3outm7_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw8
RAM16x4Q0outm8_0
RAM16x4Q1outm8_1
RAM16x4Q2outm8_2
RAM16x4Q3outm8_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw9
RAM16x4Q0outm9_0
RAM16x4Q1outm9_1
RAM16x4Q2outm9_2
RAM16x4Q3outm9_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw10
RAM16x4Q0outm10_0
RAM16x4Q1outm10_1
RAM16x4Q2outm10_2
RAM16x4Q3outm10_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw11
RAM16x4Q0outm11_0
RAM16x4Q1outm11_1
RAM16x4Q2outm11_2
RAM16x4Q3outm11_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw12
RAM16x4Q0outm12_0
RAM16x4Q1outm12_1
RAM16x4Q2outm12_2
RAM16x4Q3outm12_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw13
RAM16x4Q0outm13_0
RAM16x4Q1outm13_1
RAM16x4Q2outm13_2
RAM16x4Q3outm13_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw14
RAM16x4Q0outm14_0
RAM16x4Q1outm14_1
RAM16x4Q2outm14_2
RAM16x4Q3outm14_3
RAM16x4A0inA0
RAM16x4A1inA1
RAM16x4A2inA2
RAM16x4A3inA3
RAM16x4D0inD0
RAM16x4D1inD1
RAM16x4D2inD2
RAM16x4D3inD3
RAM16x4WEinw15
RAM16x4Q0outm15_0
RAM16x4Q1outm15_1
RAM16x4Q2outm15_2
RAM16x4Q3outm15_3
ANDI0inm0_0
ANDI1inb0
ANDO0outc0_0
ANDI0inm0_1
ANDI1inb0
ANDO0outc0_1
ANDI0inm0_2
ANDI1inb0
ANDO0outc0_2
ANDI0inm0_3
ANDI1inb0
ANDO0outc0_3
ANDI0inm1_0
ANDI1inb1
ANDO0outc1_0
ANDI0inm1_1
ANDI1inb1
ANDO0outc1_1
ANDI0inm1_2
ANDI1inb1
ANDO0outc1_2
ANDI0inm1_3
ANDI1inb1
ANDO0outc1_3
ANDI0inm2_0
ANDI1inb2
ANDO0outc2_0
ANDI0inm2_1
ANDI1inb2
ANDO0outc2_1
ANDI0inm2_2
ANDI1inb2
ANDO0outc2_2
ANDI0inm2_3
ANDI1inb2
ANDO0outc2_3
ANDI0inm3_0
ANDI1inb3
ANDO0outc3_0
ANDI0inm3_1
ANDI1inb3
ANDO0outc3_1
ANDI0inm3_2
ANDI1inb3
ANDO0outc3_2
ANDI0inm3_3
ANDI1inb3
ANDO0outc3_3
ANDI0inm4_0
ANDI1inb4
ANDO0outc4_0
ANDI0inm4_1
ANDI1inb4
ANDO0outc4_1
ANDI0inm4_2
ANDI1inb4
ANDO0outc4_2
ANDI0inm4_3
ANDI1inb4
ANDO0outc4_3
ANDI0inm5_0
ANDI1inb5
ANDO0outc5_0
ANDI0inm5_1
ANDI1inb5
ANDO0outc5_1
ANDI0inm5_2
ANDI1inb5
ANDO0outc5_2
ANDI0inm5_3
ANDI1inb5
ANDO0outc5_3
ANDI0inm6_0
ANDI1inb6
ANDO0outc6_0
ANDI0inm6_1
ANDI1inb6
ANDO0outc6_1
ANDI0inm6_2
ANDI1inb6
ANDO0outc6_2
ANDI0inm6_3
ANDI1inb6
ANDO0outc6_3
ANDI0inm7_0
ANDI1inb7
ANDO0outc7_0
ANDI0inm7_1
ANDI1inb7
ANDO0outc7_1
ANDI0inm7_2
ANDI1inb7
ANDO0outc7_2
ANDI0inm7_3
ANDI1inb7
ANDO0outc7_3
ANDI0inm8_0
ANDI1inb8
ANDO0outc8_0
ANDI0inm8_1
ANDI1inb8
ANDO0outc8_1
ANDI0inm8_2
ANDI1inb8
ANDO0outc8_2
ANDI0inm8_3
ANDI1inb8
ANDO0outc8_3
ANDI0inm9_0
ANDI1inb9
ANDO0outc9_0
ANDI0inm9_1
ANDI1inb9
ANDO0outc9_1
ANDI0inm9_2
ANDI1inb9
ANDO0outc9_2
ANDI0inm9_3
ANDI1inb9
ANDO0outc9_3
ANDI0inm10_0
ANDI1inb10
ANDO0outc10_0
ANDI0inm10_1
ANDI1inb10
ANDO0outc10_1
ANDI0inm10_2
ANDI1inb10
ANDO0outc10_2
ANDI0inm10_3
ANDI1inb10
ANDO0outc10_3
ANDI0inm11_0
ANDI1inb11
ANDO0outc11_0
ANDI0inm11_1
ANDI1inb11
ANDO0outc11_1
ANDI0inm11_2
ANDI1inb11
ANDO0outc11_2
ANDI0inm11_3
ANDI1inb11
ANDO0outc11_3
ANDI0inm12_0
ANDI1inb12
ANDO0outc12_0
ANDI0inm12_1
ANDI1inb12
ANDO0outc12_1
ANDI0inm12_2
ANDI1inb12
ANDO0outc12_2
ANDI0inm12_3
ANDI1inb12
ANDO0outc12_3
ANDI0inm13_0
ANDI1inb13
ANDO0outc13_0
ANDI0inm13_1
ANDI1inb13
ANDO0outc13_1
ANDI0inm13_2
ANDI1inb13
ANDO0outc13_2
ANDI0inm13_3
ANDI1inb13
ANDO0outc13_3
ANDI0inm14_0
ANDI1inb14
ANDO0outc14_0
ANDI0inm14_1
ANDI1inb14
ANDO0outc14_1
ANDI0inm14_2
ANDI1inb14
ANDO0outc14_2
ANDI0inm14_3
ANDI1inb14
ANDO0outc14_3
ANDI0inm15_0
ANDI1inb15
ANDO0outc15_0
ANDI0inm15_1
ANDI1inb15
ANDO0outc15_1
ANDI0inm15_2
ANDI1inb15
ANDO0outc15_2
ANDI0inm15_3
ANDI1inb15
ANDO0outc15_3
OR4Ainc0_0
OR4Binc1_0
OR4Cinc2_0
OR4Dinc3_0
OR4Youtg0_0
OR4Ainc4_0
OR4Binc5_0
OR4Cinc6_0
OR4Dinc7_0
OR4Youtg1_0
OR4Ainc8_0
OR4Binc9_0
OR4Cinc10_0
OR4Dinc11_0
OR4Youtg2_0
OR4Ainc12_0
OR4Binc13_0
OR4Cinc14_0
OR4Dinc15_0
OR4Youtg3_0
OR4Aing0_0
OR4Bing1_0
OR4Cing2_0
OR4Ding3_0
OR4YoutQ0
OR4Ainc0_1
OR4Binc1_1
OR4Cinc2_1
OR4Dinc3_1
OR4Youtg0_1
OR4Ainc4_1
OR4Binc5_1
OR4Cinc6_1
OR4Dinc7_1
OR4Youtg1_1
OR4Ainc8_1
OR4Binc9_1
OR4Cinc10_1
OR4Dinc11_1
OR4Youtg2_1
OR4Ainc12_1
OR4Binc13_1
OR4Cinc14_1
OR4Dinc15_1
OR4Youtg3_1
OR4Aing0_1
OR4Bing1_1
OR4Cing2_1
OR4Ding3_1
OR4YoutQ1
OR4Ainc0_2
OR4Binc1_2
OR4Cinc2_2
OR4Dinc3_2
OR4Youtg0_2
OR4Ainc4_2
OR4Binc5_2
OR4Cinc6_2
OR4Dinc7_2
OR4Youtg1_2
OR4Ainc8_2
OR4Binc9_2
OR4Cinc10_2
OR4Dinc11_2
OR4Youtg2_2
OR4Ainc12_2
OR4Binc13_2
OR4Cinc14_2
OR4Dinc15_2
OR4Youtg3_2
OR4Aing0_2
OR4Bing1_2
OR4Cing2_2
OR4Ding3_2
OR4YoutQ2
OR4Ainc0_3
OR4Binc1_3
OR4Cinc2_3
OR4Dinc3_3
OR4Youtg0_3
OR4Ainc4_3
OR4Binc5_3
OR4Cinc6_3
OR4Dinc7_3
OR4Youtg1_3
OR4Ainc8_3
OR4Binc9_3
OR4Cinc10_3
OR4Dinc11_3
OR4Youtg2_3
OR4Ainc12_3
OR4Binc13_3
OR4Cinc14_3
OR4Dinc15_3
OR4Youtg3_3
OR4Aing0_3
OR4Bing1_3
OR4Cing2_3
OR4Ding3_3
OR4YoutQ3

Select all → Ctrl+G → in the Library double-click the chip name → RAM256x4.

Step 3. The test bench

What we build. Eight address switches, four data switches, a WE button, three displays.

ElementPinDirectionLabel
poweroutoutVCC
groundoutoutGND
inputOutoutmA0
inputOutoutmA1
inputOutoutmA2
inputOutoutmA3
inputOutoutmA4
inputOutoutmA5
inputOutoutmA6
inputOutoutmA7
inputOutoutmD0
inputOutoutmD1
inputOutoutmD2
inputOutoutmD3
buttonoutoutmWE
RAM256x4A0inmA0
RAM256x4A1inmA1
RAM256x4A2inmA2
RAM256x4A3inmA3
RAM256x4A4inmA4
RAM256x4A5inmA5
RAM256x4A6inmA6
RAM256x4A7inmA7
RAM256x4D0inmD0
RAM256x4D1inmD1
RAM256x4D2inmD2
RAM256x4D3inmD3
RAM256x4WEinmWE
RAM256x4Q0outmQ0
RAM256x4Q1outmQ1
RAM256x4Q2outmQ2
RAM256x4Q3outmQ3

Displays: address — ⚙ width 8, HEX, bus mA; data — width 4, HEX, bus mD; memory — width 4, HEX, bus mQ. Don't group into a chip.

3.4. Check

The address on the display is two hex digits: the left one is the block (A7–A4), the right one is the cell in the block (A3–A0).

#What you doAddress mADataDisplay: address/data/memory
1address 00, value 1, WE0000 0000000100 / 1 / 1
2address 01, value 2, WE0000 0001001001 / 2 / 2
3address 10 (block 1, cell 0), 3, WE0001 0000001110 / 3 / 3
4address FF (the last), 9, WE1111 11111001FF / 9 / 9
5read address 000000 0000100100 / 9 / 1
6read address 100001 0000100110 / 9 / 3
7read address 010000 0001100101 / 9 / 2
8read address FF1111 11111001FF / 9 / 9

Step 6 is the key one: addresses 00 and 10 have the same low bits (cell 0), but different blocks — the memory doesn't mix them up.

If not:

You seeWhere to look
00 and 10 show the same thingblock DEC16: I0–I3 = A4–A7 (high bits), not A0–A3
a write spoils all blocks at onceWE of block N = wN = AND(bN, WE), not a shared WE
garbage / orange is read"pass": AND(mN_i, bN) before the OR tree

Lesson 3 paste (Cmd+I)

First step 1 (delete lesson 2's test bench), then the paste.

chip RAM256x4 {  portIn(A0)  portIn(A1)  portIn(A2)  portIn(A3)  portIn(A4)  portIn(A5)  portIn(A6)  portIn(A7)  portIn(D0)  portIn(D1)  portIn(D2)  portIn(D3)  portIn(WE)  portOut(Q0)  portOut(Q1)  portOut(Q2)  portOut(Q3)  DEC16(I0=A4, I1=A5, I2=A6, I3=A7, Y0=b0, Y1=b1, Y2=b2, Y3=b3, Y4=b4, Y5=b5, Y6=b6, Y7=b7, Y8=b8, Y9=b9, Y10=b10, Y11=b11, Y12=b12, Y13=b13, Y14=b14, Y15=b15)  AND(b0, WE, w0)  AND(b1, WE, w1)  AND(b2, WE, w2)  AND(b3, WE, w3)  AND(b4, WE, w4)  AND(b5, WE, w5)  AND(b6, WE, w6)  AND(b7, WE, w7)  AND(b8, WE, w8)  AND(b9, WE, w9)  AND(b10, WE, w10)  AND(b11, WE, w11)  AND(b12, WE, w12)  AND(b13, WE, w13)  AND(b14, WE, w14)  AND(b15, WE, w15)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w0, Q0=m0_0, Q1=m0_1, Q2=m0_2, Q3=m0_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w1, Q0=m1_0, Q1=m1_1, Q2=m1_2, Q3=m1_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w2, Q0=m2_0, Q1=m2_1, Q2=m2_2, Q3=m2_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w3, Q0=m3_0, Q1=m3_1, Q2=m3_2, Q3=m3_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w4, Q0=m4_0, Q1=m4_1, Q2=m4_2, Q3=m4_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w5, Q0=m5_0, Q1=m5_1, Q2=m5_2, Q3=m5_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w6, Q0=m6_0, Q1=m6_1, Q2=m6_2, Q3=m6_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w7, Q0=m7_0, Q1=m7_1, Q2=m7_2, Q3=m7_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w8, Q0=m8_0, Q1=m8_1, Q2=m8_2, Q3=m8_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w9, Q0=m9_0, Q1=m9_1, Q2=m9_2, Q3=m9_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w10, Q0=m10_0, Q1=m10_1, Q2=m10_2, Q3=m10_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w11, Q0=m11_0, Q1=m11_1, Q2=m11_2, Q3=m11_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w12, Q0=m12_0, Q1=m12_1, Q2=m12_2, Q3=m12_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w13, Q0=m13_0, Q1=m13_1, Q2=m13_2, Q3=m13_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w14, Q0=m14_0, Q1=m14_1, Q2=m14_2, Q3=m14_3)  RAM16x4(A0=A0, A1=A1, A2=A2, A3=A3, D0=D0, D1=D1, D2=D2, D3=D3, WE=w15, Q0=m15_0, Q1=m15_1, Q2=m15_2, Q3=m15_3)  AND(m0_0, b0, c0_0)  AND(m0_1, b0, c0_1)  AND(m0_2, b0, c0_2)  AND(m0_3, b0, c0_3)  AND(m1_0, b1, c1_0)  AND(m1_1, b1, c1_1)  AND(m1_2, b1, c1_2)  AND(m1_3, b1, c1_3)  AND(m2_0, b2, c2_0)  AND(m2_1, b2, c2_1)  AND(m2_2, b2, c2_2)  AND(m2_3, b2, c2_3)  AND(m3_0, b3, c3_0)  AND(m3_1, b3, c3_1)  AND(m3_2, b3, c3_2)  AND(m3_3, b3, c3_3)  AND(m4_0, b4, c4_0)  AND(m4_1, b4, c4_1)  AND(m4_2, b4, c4_2)  AND(m4_3, b4, c4_3)  AND(m5_0, b5, c5_0)  AND(m5_1, b5, c5_1)  AND(m5_2, b5, c5_2)  AND(m5_3, b5, c5_3)  AND(m6_0, b6, c6_0)  AND(m6_1, b6, c6_1)  AND(m6_2, b6, c6_2)  AND(m6_3, b6, c6_3)  AND(m7_0, b7, c7_0)  AND(m7_1, b7, c7_1)  AND(m7_2, b7, c7_2)  AND(m7_3, b7, c7_3)  AND(m8_0, b8, c8_0)  AND(m8_1, b8, c8_1)  AND(m8_2, b8, c8_2)  AND(m8_3, b8, c8_3)  AND(m9_0, b9, c9_0)  AND(m9_1, b9, c9_1)  AND(m9_2, b9, c9_2)  AND(m9_3, b9, c9_3)  AND(m10_0, b10, c10_0)  AND(m10_1, b10, c10_1)  AND(m10_2, b10, c10_2)  AND(m10_3, b10, c10_3)  AND(m11_0, b11, c11_0)  AND(m11_1, b11, c11_1)  AND(m11_2, b11, c11_2)  AND(m11_3, b11, c11_3)  AND(m12_0, b12, c12_0)  AND(m12_1, b12, c12_1)  AND(m12_2, b12, c12_2)  AND(m12_3, b12, c12_3)  AND(m13_0, b13, c13_0)  AND(m13_1, b13, c13_1)  AND(m13_2, b13, c13_2)  AND(m13_3, b13, c13_3)  AND(m14_0, b14, c14_0)  AND(m14_1, b14, c14_1)  AND(m14_2, b14, c14_2)  AND(m14_3, b14, c14_3)  AND(m15_0, b15, c15_0)  AND(m15_1, b15, c15_1)  AND(m15_2, b15, c15_2)  AND(m15_3, b15, c15_3)  OR4(A=c0_0, B=c1_0, C=c2_0, D=c3_0, Y=g0_0)  OR4(A=c4_0, B=c5_0, C=c6_0, D=c7_0, Y=g1_0)  OR4(A=c8_0, B=c9_0, C=c10_0, D=c11_0, Y=g2_0)  OR4(A=c12_0, B=c13_0, C=c14_0, D=c15_0, Y=g3_0)  OR4(A=g0_0, B=g1_0, C=g2_0, D=g3_0, Y=Q0)  OR4(A=c0_1, B=c1_1, C=c2_1, D=c3_1, Y=g0_1)  OR4(A=c4_1, B=c5_1, C=c6_1, D=c7_1, Y=g1_1)  OR4(A=c8_1, B=c9_1, C=c10_1, D=c11_1, Y=g2_1)  OR4(A=c12_1, B=c13_1, C=c14_1, D=c15_1, Y=g3_1)  OR4(A=g0_1, B=g1_1, C=g2_1, D=g3_1, Y=Q1)  OR4(A=c0_2, B=c1_2, C=c2_2, D=c3_2, Y=g0_2)  OR4(A=c4_2, B=c5_2, C=c6_2, D=c7_2, Y=g1_2)  OR4(A=c8_2, B=c9_2, C=c10_2, D=c11_2, Y=g2_2)  OR4(A=c12_2, B=c13_2, C=c14_2, D=c15_2, Y=g3_2)  OR4(A=g0_2, B=g1_2, C=g2_2, D=g3_2, Y=Q2)  OR4(A=c0_3, B=c1_3, C=c2_3, D=c3_3, Y=g0_3)  OR4(A=c4_3, B=c5_3, C=c6_3, D=c7_3, Y=g1_3)  OR4(A=c8_3, B=c9_3, C=c10_3, D=c11_3, Y=g2_3)  OR4(A=c12_3, B=c13_3, C=c14_3, D=c15_3, Y=g3_3)  OR4(A=g0_3, B=g1_3, C=g2_3, D=g3_3, Y=Q3)} power(VCC)ground(GND)input(Out=mA0)input(Out=mA1)input(Out=mA2)input(Out=mA3)input(Out=mA4)input(Out=mA5)input(Out=mA6)input(Out=mA7)input(Out=mD0)input(Out=mD1)input(Out=mD2)input(Out=mD3)button{label="WE", hostKey="KeyW"}(mWE)RAM256x4(A0=mA0, A1=mA1, A2=mA2, A3=mA3, A4=mA4, A5=mA5, A6=mA6, A7=mA7, D0=mD0, D1=mD1, D2=mD2, D3=mD3, WE=mWE, Q0=mQ0, Q1=mQ1, Q2=mQ2, Q3=mQ3)display{bits=8, base="HEX", busSource="mA"}()display{bits=4, base="HEX", busSource="mD"}()display{bits=4, base="HEX", busSource="mQ"}()

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