Lesson 5. Two-phase clock: the write never meets a new address

After this lesson the game runs on your memory without errors — in Fast and in REAL. For this the processor will do every instruction in two phases: in the first, the address and the instruction are set up; in the second, the write happens. That's how real processors work: the Intel 8080 and the MOS 6502 have two clocks, φ1 and φ2.

5.1. The idea: put "new address" and "write" into different slices

From lesson 4: the trouble is that the write window opens and closes on the same edges where the address changes. The solution is to give each instruction two periods of the fast clock:

• divide by 2: a DFF whose nQ goes back to its D input flips on every CPUCLK edge — this gives the slow clock CLK2;
• all the registers of the processor (PC, accumulator, flags, stack, display latches — 28 of them) step on CLK2: phase ① — the address and the instruction change and settle;
• the write window weRAM = AND3(oST, nCLK2, CPUCLK) — phase ②: the second half of CLK2, and only while CPUCLK = 1. It closes half a CPUCLK period before CLK2 moves PC;
• an AND with nRST holds the divider at 0 during reset: otherwise at power-on it sits at "nothing", like any latch.

NOT CLK2 comes from the flip-flop itself (pin nQ) — no separate NOT is needed.

5.2. Why it doesn't break now

The oscilloscope shows it: the address changes in one slice, the window opens one slice later and closes two slices before the next address change. There is not a single slice where a "new address" and an "open window" happen at the same time.

The cost. An instruction takes two CPUCLK periods — the processor has become twice as slow. On the last levels of the game a step may not keep up; it's more comfortable to play in Fast.

5.3. Building

Everything is inside GW-CPU ("Edit"). The chip's pins and everything outside stay unchanged.

Step 1. Delete lesson 4's window

Step 2. The divider and the new window

What we build. A reset NOT, the divider's AND, a DFF and the window's AND3. The AND3 output is the weRAM label again, so the memory's WE doesn't need to be reconnected.

Step 3. Registers on CLK2

Each of the 28 registers has its own CPUCLK label on its CLK pin — double-click it and rename it to CLK2.

⚠ One of these labels is also connected by a wire to the chip's CPUCLK port pin. Don't rename that one: on that register cut the wire from it and put a new CLK2 label on CLK. Otherwise the chip's input will move to CLK2, and the divider will stop dividing.

The CPUCLK port and the CPUCLK labels on the DFF and the AND3 stay on CPUCLK.

5.4. Check

Engine Fast, clock MAX, the program is the same game-myram.rom.json.

If not:

Lesson 5 paste (Cmd+I)

In GW-CPU edit mode, after step 1. Step 3 (28 labels) — by hand.

NOT(RST, nRST)AND(nCLK2, nRST, dCLK2)DFF(D=dCLK2, CLK=CPUCLK, Q=CLK2, nQ=nCLK2) AND3(oST, nCLK2, CPUCLK, weRAM)